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path: root/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
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* Silencing an MSVC warning about signed vs unsigned comparison mismatches.Aaron Ballman2013-07-171-1/+1
| | | | llvm-svn: 186529
* [SystemZ] Use ROSBG and non-zero form of RISBG for OR nodesRichard Sandiford2013-07-161-1/+86
| | | | llvm-svn: 186405
* [SystemZ] Use RISBG for (shift (and ...))Richard Sandiford2013-07-161-97/+168
| | | | | | | Another patch in the series to make more use of R.SBG. This one extends r186072 and r186073 to handle cases where the AND is inside the shift. llvm-svn: 186399
* [SystemZ] Use zeroing form of RISBG for shift-and-AND sequencesRichard Sandiford2013-07-111-5/+66
| | | | | | Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
* [SystemZ] Use zeroing form of RISBG for some AND sequencesRichard Sandiford2013-07-111-1/+118
| | | | | | | | | | | | RISBG can handle some ANDs for which no AND IMMEDIATE exists. It also acts as a three-operand AND for some cases where an AND IMMEDIATE could be used instead. It might be worth adding a pass to replace RISBG with AND IMMEDIATE in cases where the register operands end up being the same and where AND IMMEDIATE is smaller. llvm-svn: 186072
* [SystemZ] Use MVC for simple load/store pairsRichard Sandiford2013-07-091-0/+46
| | | | | | | | | | | | Look for patterns of the form (store (load ...), ...) in which the two locations are known not to partially overlap. (Identical locations are OK.) These sequences are better implemented by MVC unless either the load or the store could use RELATIVE LONG instructions. The testcase showed that we weren't using LHRL and LGHRL for extload16, only sextloadi16. The patch fixes that too. llvm-svn: 185919
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-2/+2
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* [SystemZ] Add back endUlrich Weigand2013-05-061-0/+616
| | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
* Remove the SystemZ backend.Dan Gohman2011-10-241-779/+0
| | | | llvm-svn: 142878
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-15/+14
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* zap dead code.Chris Lattner2010-09-041-2/+0
| | | | llvm-svn: 113073
* Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen2010-05-281-2/+2
| | | | | | | | | | were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. llvm-svn: 105063
* Use enums instead of literals for SystemZ subregistersJakob Stoklund Olesen2010-05-251-11/+11
| | | | llvm-svn: 104612
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-3/+2
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Sink InstructionSelect() out of each target into SDISel, and rename itChris Lattner2010-03-021-49/+7
| | | | | | | | | | | | DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) llvm-svn: 97555
* Split SelectionDAGISel::IsLegalAndProfitableToFold toEvan Cheng2010-02-151-2/+1
| | | | | | | | IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use. This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses. llvm-svn: 96255
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-8/+8
| | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. llvm-svn: 95687
* Change SelectCode's argument from SDValue to SDNode *, to make it moreDan Gohman2010-01-051-32/+31
| | | | | | | | | clear what information these functions are actually using. This is also a micro-optimization, as passing a SDNode * around is simpler than passing a { SDNode *, int } by value or reference. llvm-svn: 92564
* Fix invalid chain folding for memory variant of sdiv / udivAnton Korobeynikov2010-01-041-26/+26
| | | | llvm-svn: 92472
* Remove uninteresting and confusing debug output.Dan Gohman2009-11-051-2/+0
| | | | llvm-svn: 86149
* Rename getTargetNode to getMachineNode, for consistency with theDan Gohman2009-09-251-37/+38
| | | | | | | | naming scheme used in SelectionDAG, where there are multiple kinds of "target" nodes, but "machine" nodes are nodes which represent a MachineInstr. llvm-svn: 82790
* Fix some refactos for iostream changes (in -Asserts mode).Daniel Dunbar2009-08-231-4/+4
| | | | | | - The world needs better C++ refactoring tools, can I get an Amen!? llvm-svn: 79843
* eliminate uses of cerr()Chris Lattner2009-08-231-9/+11
| | | | llvm-svn: 79834
* eliminate the last DOUTs from the targets.Chris Lattner2009-08-231-49/+32
| | | | llvm-svn: 79833
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-21/+21
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-27/+27
| | | | | | own struct type. llvm-svn: 78610
* Fix 'may be used uninitialized' warning.Daniel Dunbar2009-07-171-2/+2
| | | | | | - Anton, please review. llvm-svn: 76144
* UnbreakAnton Korobeynikov2009-07-161-0/+1
| | | | llvm-svn: 76064
* Fix logic inversion for RI-mode address selectionAnton Korobeynikov2009-07-161-1/+1
| | | | llvm-svn: 76052
* Unbreak mvi and friends - emit only 'significant' part of the operandAnton Korobeynikov2009-07-161-0/+6
| | | | llvm-svn: 76041
* Provide consistent subreg idx scheme. This (hopefully) fixes remaining ↵Anton Korobeynikov2009-07-161-25/+24
| | | | | | divide problems llvm-svn: 76011
* Use divide single for 32 bit signed dividesAnton Korobeynikov2009-07-161-10/+24
| | | | llvm-svn: 76010
* Remove redundand register moveAnton Korobeynikov2009-07-161-21/+7
| | | | llvm-svn: 76004
* Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov2009-07-161-0/+206
| | | | llvm-svn: 76003
* 32 bit shifts have only 12 bit displacementsAnton Korobeynikov2009-07-161-3/+13
| | | | llvm-svn: 76000
* TyposAnton Korobeynikov2009-07-161-2/+2
| | | | llvm-svn: 75991
* Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.Anton Korobeynikov2009-07-161-160/+120
| | | | llvm-svn: 75990
* Add support for 12 bit displacementsAnton Korobeynikov2009-07-161-44/+108
| | | | llvm-svn: 75988
* 32-bit ri addressing mode has only 12-bit displacementAnton Korobeynikov2009-07-161-0/+84
| | | | llvm-svn: 75973
* Swap the order of imm and idx field for rri addrmode in order to make ↵Anton Korobeynikov2009-07-161-6/+6
| | | | | | handling of rri and ri addrmodes common llvm-svn: 75937
* Do not truncate sign bits for negative immsAnton Korobeynikov2009-07-161-18/+20
| | | | llvm-svn: 75936
* Add address computation stuffAnton Korobeynikov2009-07-161-3/+63
| | | | llvm-svn: 75935
* Add stores and truncstoresAnton Korobeynikov2009-07-161-3/+4
| | | | llvm-svn: 75931
* Add patterns for various extloadsAnton Korobeynikov2009-07-161-0/+3
| | | | llvm-svn: 75930
* Do some heroic rri address matching (shamelessly stolen from x86 backend). ↵Anton Korobeynikov2009-07-161-11/+230
| | | | | | Not tested though. llvm-svn: 75929
* Add shifts and reg-imm address matchingAnton Korobeynikov2009-07-161-0/+87
| | | | llvm-svn: 75927
* Add bunch of reg-imm movsAnton Korobeynikov2009-07-161-0/+6
| | | | llvm-svn: 75921
* Provide masked reg-imm 'or' and 'and'Anton Korobeynikov2009-07-161-1/+7
| | | | llvm-svn: 75919
* Let's start another backend :)Anton Korobeynikov2009-07-161-0/+129
llvm-svn: 75909
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