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path: root/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
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* Remove the local subtarget variable from the SystemZ asm printerEric Christopher2015-02-191-2/+2
| | | | | | and update the two calls accordingly. llvm-svn: 229805
* [SystemZ] Support all TLS access models - CodeGen partUlrich Weigand2015-02-181-0/+37
| | | | | | | | | | | | | | | | | | | | | | The current SystemZ back-end only supports the local-exec TLS access model. This patch adds all required CodeGen support for the other TLS models, which means in particular: - Expand initial-exec TLS accesses by loading TLS offsets from the GOT using @indntpoff relocations. - Expand general-dynamic and local-dynamic accesses by generating the appropriate calls to __tls_get_offset. Note that this routine has a non-standard ABI and requires loading the GOT pointer into %r12, so the patch also adds support for the GLOBAL_OFFSET_TABLE ISD node. - Add a new platform-specific optimization pass to remove redundant __tls_get_offset calls in the local-dynamic model (modeled after the corresponding X86 pass). - Add test cases verifying all access models and optimizations. llvm-svn: 229654
* Move DataLayout back to the TargetMachine from TargetSubtargetInfoEric Christopher2015-01-261-3/+2
| | | | | | | | | | | | | | | | | | | derived classes. Since global data alignment, layout, and mangling is often based on the DataLayout, move it to the TargetMachine. This ensures that global data is going to be layed out and mangled consistently if the subtarget changes on a per function basis. Prior to this all targets(*) have had subtarget dependent code moved out and onto the TargetMachine. *One target hasn't been migrated as part of this change: R600. The R600 port has, as a subtarget feature, the size of pointers and this affects global data layout. I've currently hacked in a FIXME to enable progress, but the port needs to be updated to either pass the 64-bitness to the TargetMachine, or fix the DataLayout to avoid subtarget dependent features. llvm-svn: 227113
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+3
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [SystemZ] Use "auto" for cast resultsRichard Sandiford2014-03-061-3/+2
| | | | | | No functional change intended. llvm-svn: 203106
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+1
| | | | llvm-svn: 200345
* Move the llvm mangler to lib/IR.Rafael Espindola2014-01-071-1/+1
| | | | | | This makes it available to tools that don't link with target (like llvm-ar). llvm-svn: 198708
* Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford2013-12-101-0/+9
| | | | | | | | | | | | | | | | | One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. llvm-svn: 196905
* [SystemZ] Fix TMHH and TMHL usage for z10 with -O0Richard Sandiford2013-11-221-8/+22
| | | | | | | | | | | | I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. llvm-svn: 195473
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-291-1/+1
| | | | llvm-svn: 193627
* The AsmPrinter has a Mangler. Use it.Rafael Espindola2013-10-291-2/+2
| | | | llvm-svn: 193617
* [SystemZ] Allow integer AND involving high wordsRichard Sandiford2013-10-011-0/+3
| | | | llvm-svn: 191762
* [SystemZ] Allow integer XOR involving high wordsRichard Sandiford2013-10-011-0/+1
| | | | llvm-svn: 191759
* [SystemZ] Allow integer OR involving high wordsRichard Sandiford2013-10-011-0/+3
| | | | llvm-svn: 191755
* [SystemZ] Allow integer insertions with a high-word destinationRichard Sandiford2013-10-011-0/+17
| | | | llvm-svn: 191753
* [SystemZ] Add patterns to load a constant into a high word (IIHF)Richard Sandiford2013-10-011-0/+6
| | | | | | | Similar to low words, we can use the shorter LLIHL and LLIHH if it turns out that the other half of the GR64 isn't live. llvm-svn: 191750
* [SystemZ] Use upper words of GR64s for codegenRichard Sandiford2013-10-011-0/+22
| | | | | | | | | | | | | | This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. llvm-svn: 191739
* [SystemZ] Define the GR64 low-word logic instructions as pseudo aliases.Richard Sandiford2013-09-251-0/+30
| | | | | | | | Another patch to avoid duplication of encoding information. Things like NILF, NILL and NILH are used as both 32-bit and 64-bit instructions. Here the 64-bit versions are defined as aliases of the 32-bit ones. llvm-svn: 191369
* [SystemZ] Define the call instructions as pseudo aliases.Richard Sandiford2013-09-251-1/+23
| | | | | | | | Similar to r191364, but for calls. This patch also removes the shortening of BRASL to BRAS within a TU. Doing that was a bit controversial internally, since there's a strong expectation with the z assembler that WYWIWYG. llvm-svn: 191366
* [SystemZ] Define the return instruction as a pseudo alias of BRRichard Sandiford2013-09-251-2/+10
| | | | | | | | This is the first of a few patches to reduce the dupliation of encoding information. The return instruction is a normal BR in which one of the registers is fixed. llvm-svn: 191364
* Remove address spaces from MC.Rafael Espindola2013-07-021-1/+1
| | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). llvm-svn: 185436
* [SystemZ] Add back endUlrich Weigand2013-05-061-0/+113
| | | | | | | | | | | | | | This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
* Remove the SystemZ backend.Dan Gohman2011-10-241-221/+0
| | | | llvm-svn: 142878
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-3/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Fix imm printing for logical instructions.Anton Korobeynikov2011-02-011-0/+6
| | | | | | Patch by Brian G. Lucas! llvm-svn: 124679
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-141-0/+217
that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
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