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* [SystemZ] Add z13 vector facility and MC supportUlrich Weigand2015-05-051-31/+93
| | | | | | | | | | | | | | | | | | | | | This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
* [SystemZ] Clean up AsmParser isMem() handlingUlrich Weigand2015-05-041-35/+41
| | | | | | | | | | | | We know what MemoryKind an operand has at the time we construct it, so we might as well just record it in an unused part of the structure. This makes it easier to add scatter/gather addresses later. No behavioral change intended. Patch originally by Richard Sandiford. llvm-svn: 236432
* [SystemZ] Support all TLS access models - MC partUlrich Weigand2015-02-181-6/+87
| | | | | | | | | | | | | | | | | | | | | | | The current SystemZ back-end only supports the local-exec TLS access model. This patch adds all required MC support for the other TLS models, which means in particular: - Support additional relocation types for Initial-exec model: R_390_TLS_IEENT Local-dynamic-model: R_390_TLS_LDO32, R_390_TLS_LDO64, R_390_TLS_LDM32, R_390_TLS_LDM64, R_390_TLS_LDCALL General-dynamic model: R_390_TLS_GD32, R_390_TLS_GD64, R_390_TLS_GDCALL - Support assembler syntax to generate additional relocations for use with __tls_get_offset calls: :tls_gdcall: :tls_ldcall: The patch also adds a new test to verify fixups and relocations, and removes the (already unused) FK_390_PLT16DBL/FK_390_PLT32DBL fixup kinds. llvm-svn: 229652
* Minor cleanup to all the switches after MatchInstructionImpl in all the ↵Craig Topper2015-01-031-1/+0
| | | | | | | | AsmParsers. Make sure they all have llvm_unreachable on the default path out of the switch. Remove unnecessary "default: break". Remove a 'return' after unreachable. Fix some indentation. llvm-svn: 225114
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-181-4/+4
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* AsmMatchers: Use unique_ptr to manage ownership of MCParsedAsmOperandDavid Blaikie2014-06-081-99/+73
| | | | | | | | | | | | I saw at least a memory leak or two from inspection (on probably untested error paths) and r206991, which was the original inspiration for this change. I ran this idea by Jim Grosbach a few weeks ago & he was OK with it. Since it's a basically mechanical patch that seemed sufficient - usual post-commit review, revert, etc, as needed. llvm-svn: 210427
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-4/+4
| | | | llvm-svn: 207197
* Create MCTargetOptions.Evgeniy Stepanov2014-04-231-1/+2
| | | | | | | | | For now it contains a single flag, SanitizeAddress, which enables AddressSanitizer instrumentation of inline assembly. Patch by Yuri Gorshenin. llvm-svn: 206971
* LLVMBuild.txt: Reformat.NAKAMURA Takumi2014-04-101-1/+1
| | | | llvm-svn: 205961
* [SystemZ] Remove "virtual" from override methodsRichard Sandiford2014-03-061-20/+18
| | | | | | | Also fix a couple of cases where "override" was missing. No behavioural change intended. llvm-svn: 203110
* [SystemZ] Use "auto" for cast resultsRichard Sandiford2014-03-061-3/+3
| | | | | | No functional change intended. llvm-svn: 203106
* [SystemZ] Update namespace formatting to match current guidelinesRichard Sandiford2014-03-061-1/+1
| | | | | | No functional change intended. llvm-svn: 203103
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-021-15/+15
| | | | llvm-svn: 202621
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-281-1/+1
| | | | llvm-svn: 200345
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi2013-11-281-2/+0
| | | | | | I forgot to commit them. They were staging in my local repo. llvm-svn: 195924
* [SystemZ] Use upper words of GR64s for codegenRichard Sandiford2013-10-011-0/+5
| | | | | | | | | | | | | | This just adds the basics necessary for allocating the upper words to virtual registers (move, load and store). The move support is parameterised in a way that makes it easy to handle zero extensions, but the associated zero-extend patterns are added by a later patch. The easiest way of testing this seemed to be add a new "h" register constraint for high words. I don't expect the constraint to be useful in real inline asms, but it should work, so I didn't try to hide it behind an option. llvm-svn: 191739
* [SystemZ] Add GRH32 for the high word of a GR64Richard Sandiford2013-09-301-0/+6
| | | | | | | | | The only thing this does on its own is make the definitions of RISB[HL]G a bit more precise. Those instructions are only used by the MC layer at the moment, so no behavioral change is intended. The class is needed by later patches though. llvm-svn: 191660
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* Split generated asm mnemonic matching table into a separate table for each ↵Craig Topper2013-07-241-0/+1
| | | | | | | | asm variant. This removes the need to store the asm variant in each row of the single table that existed before. Shaves ~16K off the size of X86AsmParser.o. llvm-svn: 187026
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-021-84/+119
| | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. llvm-svn: 185433
* [SystemZ] Improve AsmParser handling of invalid instructionsRichard Sandiford2013-05-241-74/+103
| | | | | | | | | | | | | | | | | | | | | | | Previously, an invalid instruction like: foo %r1, %r0 would generate the rather odd error message: ....: error: unknown token in expression foo %r1, %r0 ^ We now get the more informative: ....: error: invalid instruction foo %r1, %r0 ^ The same would happen if an address were used where a register was expected. We now get "invalid operand for instruction" instead. llvm-svn: 182644
* [SystemZ] Improve AsmParser register parsingRichard Sandiford2013-05-241-53/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to make sure that: (1) "register expected" is restricted to cases where ParseRegister() is called and the token obviously isn't a register. (2) "invalid register" is restricted to cases where a register-like "%..." sequence is found, but the "..." makes no sense. (3) the generic "invalid operand for instruction" is used in cases where the wrong register type is used (GPR instead of FPR, etc.). (4) the new "invalid register pair" is used if the register has the right type, but is not a valid register pair. Testing of (1)-(3) is now restricted to regs-bad.s. It uses a representative instruction for each register class to make sure that only registers from that class are accepted. (4) is tested by both regs-bad.s (which checks all invalid register pairs) and insn-bad.s (which tests one invalid pair for each instruction that requires a pair). While there, I changed "Number" to "Num" for consistency with the operand class. llvm-svn: 182643
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-141-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. llvm-svn: 181773
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-141-57/+27
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181771
* [SystemZ] Add back endUlrich Weigand2013-05-064-0/+735
This adds the actual lib/Target/SystemZ target files necessary to implement the SystemZ target. Note that at this point, the target cannot yet be built since the configure bits are missing. Those will be provided shortly by a follow-on patch. This version of the patch incorporates feedback from reviews by Chris Lattner and Anton Korobeynikov. Thanks to all reviewers! Patch by Richard Sandiford. llvm-svn: 181203
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