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* Don't use %g0 to materialize 0 directly.Jakob Stoklund Olesen2013-05-192-4/+2
| | | | | | | | The wired physreg doesn't work on tied operands like on MOVXCC. Add a README note to fix this later. llvm-svn: 182225
* Select i64 values with %icc conditions.Jakob Stoklund Olesen2013-05-191-0/+5
| | | | llvm-svn: 182224
* Add floating point selects on %xcc predicates.Jakob Stoklund Olesen2013-05-191-0/+10
| | | | llvm-svn: 182222
* Implement SPselectfcc for i64 operands.Jakob Stoklund Olesen2013-05-192-27/+31
| | | | | | | Also clean up the arguments to all the MOVCC instructions so the operands always are (true-val, false-val, cond-code). llvm-svn: 182221
* [Sparc] Rearrange integer registers' allocation order so that register ↵Venkatraman Govindaraju2013-05-192-10/+23
| | | | | | | | allocator will use I and G registers before using L and O registers. Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode. llvm-svn: 182219
* Handle i64 FrameIndex nodes in SPARC v9 mode.Jakob Stoklund Olesen2013-05-191-1/+1
| | | | llvm-svn: 182216
* [Sparc] Implements hasReservedCallFrame and hasFP.Venkatraman Govindaraju2013-05-172-1/+17
| | | | | | | This is to generate correct framesetup code when the function has variable sized allocas. llvm-svn: 182108
* [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay ↵Venkatraman Govindaraju2013-05-161-5/+9
| | | | | | slot. llvm-svn: 182063
* Remove the MachineMove class.Rafael Espindola2013-05-131-0/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Remove unused argument.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181618
* Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen2013-04-211-0/+47
| | | | | | | Arguments after the fixed arguments never use the floating point registers. llvm-svn: 179987
* Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen2013-04-211-2/+1
| | | | | | Don't ignore the high 32 bits of the immediate. llvm-svn: 179985
* Compile varargs functions for SPARCv9.Jakob Stoklund Olesen2013-04-201-31/+57
| | | | | | | | | | | | With a little help from the frontend, it looks like the standard va_* intrinsics can do the job. Also clean up an old bitcast hack in LowerVAARG that dealt with unaligned double loads. Load SDNodes can specify an alignment now. Still missing: Calling varargs functions with float arguments. llvm-svn: 179961
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-201-1/+0
| | | | llvm-svn: 179939
* Add 64-bit multiply and divide instructions for SPARC v9.Jakob Stoklund Olesen2013-04-162-0/+42
| | | | llvm-svn: 179582
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-144-7/+8
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Add support for the abs64 SPARC v9 code model.Jakob Stoklund Olesen2013-04-141-0/+9
| | | | | | For when 16 TB just isn't enough. llvm-svn: 179474
* Add support for the SPARC v9 abs44 code model.Jakob Stoklund Olesen2013-04-141-6/+16
| | | | | | | This is the default model for non-PIC 64-bit code. It supports text+data+bss linked anywhere in the low 16 TB of the address space. llvm-svn: 179473
* Use target flags for printing SPARC asm operands.Jakob Stoklund Olesen2013-04-141-16/+34
| | | | | | | 64-bit code models need multiple relocations that can't be inferred from the opcode like they can in 32-bit code. llvm-svn: 179472
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-142-26/+36
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Fix patterns for 64-bit pointers.Jakob Stoklund Olesen2013-04-141-4/+2
| | | | | | This fixes the pic32 code model for SPARC v9. llvm-svn: 179469
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-143-14/+95
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Define SPARC code models.Jakob Stoklund Olesen2013-04-132-4/+32
| | | | | | | Currently, only abs32 and pic32 are implemented. Add a test case for abs32 with 64-bit code. 64-bit PIC code is currently broken. llvm-svn: 179463
* Use the correct types when matching ADDRri patterns from frame indexes.Jakob Stoklund Olesen2013-04-131-3/+4
| | | | | | | It doesn't seem like anybody is checking types this late in isel, so no test case. llvm-svn: 179462
* Extract a function.Jakob Stoklund Olesen2013-04-091-31/+17
| | | | llvm-svn: 179086
* Compute correct frame sizes for SPARC v9 64-bit frames.Jakob Stoklund Olesen2013-04-093-25/+40
| | | | | | | | | | The save area is twice as big and there is no struct return slot. The stack pointer is always 16-byte aligned (after adding the bias). Also eliminate the stack adjustment instructions around calls when the function has a reserved stack frame. llvm-svn: 179083
* Implement LowerCall_64 for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-072-0/+228
| | | | | | | There is still no support for byval arguments (which I don't think are needed) and varargs. llvm-svn: 178993
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-063-9/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer return values are sign or zero extended by the callee, and structs up to 32 bytes in size can be returned in registers. The CC_Sparc64 CallingConv definition is shared between LowerFormalArguments_64 and LowerReturn_64. Function arguments and return values are passed in the same registers. The inreg flag is also used for return values. This is required to handle C functions returning structs containing floats and ints: struct ifp { int i; float f; }; struct ifp f(void); LLVM IR: define inreg { i32, float } @f() { ... ret { i32, float } %retval } The ABI requires that %retval.i is returned in the high bits of %i0 while %retval.f goes in %f1. Without the inreg return value attribute, %retval.i would go in %i0 and %retval.f would go in %f3 which is a more efficient way of returning %multiple values, but it is not ABI compliant for returning C structs. llvm-svn: 178966
* SPARC v9 stack pointer bias.Jakob Stoklund Olesen2013-04-062-2/+9
| | | | | | | | | | | 64-bit SPARC v9 processes use biased stack and frame pointers, so the current function's stack frame is located at %sp+BIAS .. %fp+BIAS where BIAS = 2047. This makes more local variables directly accessible via [%fp+simm13] addressing. llvm-svn: 178965
* Complete formal arguments for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-062-25/+178
| | | | | | | | | | | | | | | | | | | | | | | | All arguments are formally assigned to stack positions and then promoted to floating point and integer registers. Since there are more floating point registers than integer registers, this can cause situations where floating point arguments are assigned to registers after integer arguments that where assigned to the stack. Use the inreg flag to indicate 32-bit fragments of structs containing both float and int members. The three-way shadowing between stack, integer, and floating point registers requires custom argument lowering. The good news is that return values are passed in the exact same way, and we can share the code. Still missing: - Update LowerReturn to handle structs returned in registers. - LowerCall. - Variadic functions. llvm-svn: 178958
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-044-5/+35
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-035-5/+34
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Add 64-bit load and store instructions.Jakob Stoklund Olesen2013-04-021-0/+68
| | | | | | There is only a few new instructions, the rest is handled with patterns. llvm-svn: 178528
* Basic 64-bit ALU operations.Jakob Stoklund Olesen2013-04-021-0/+38
| | | | | | | SPARC v9 extends all ALU instructions to 64 bits, so we simply need to add patterns to use them for both i32 and i64 values. llvm-svn: 178527
* Materialize 64-bit immediates.Jakob Stoklund Olesen2013-04-021-0/+88
| | | | | | | The last resort pattern produces 6 instructions, and there are still opportunities for materializing some immediates in fewer instructions. llvm-svn: 178526
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-023-0/+86
| | | | | | | | | | | SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. llvm-svn: 178525
* Add predicates for distinguishing 32-bit and 64-bit modes.Jakob Stoklund Olesen2013-04-021-0/+6
| | | | | | | | | | | The 'sparc' architecture produces 32-bit code while 'sparcv9' produces 64-bit code. It is also possible to run 32-bit code using SPARC v9 instructions with: llc -march=sparc -mattr=+v9 llvm-svn: 178524
* Add support for 64-bit calling convention.Jakob Stoklund Olesen2013-04-023-11/+115
| | | | | | | | | | | | This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. llvm-svn: 178523
* Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen2013-04-026-11/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. llvm-svn: 178522
* Clean up Sparc patterns.Jakob Stoklund Olesen2013-03-241-5/+5
| | | | | | | The types of register variables no longer need to be specified in output patterns. llvm-svn: 177845
* Give Sparc instruction patterns direct types instead of register classes.Jakob Stoklund Olesen2013-03-241-81/+68
| | | | | | | Also update the documentation since Sparc is the nicest backend, and used as an example in WritingAnLLVMBackend. llvm-svn: 177835
* Use direct types in Sparc def : Pat patterns.Jakob Stoklund Olesen2013-03-231-10/+10
| | | | | | | | | | The SelectionDAG graph has MVT type labels, not register classes, so this makes it clearer what is happening. This notation is also robust against adding more types to the IntRegs register class. llvm-svn: 177829
* Provide the register scavenger to processFunctionBeforeFrameFinalizedHal Finkel2013-03-141-1/+2
| | | | | | | | | | | | | Add the current PEI register scavenger as a parameter to the processFunctionBeforeFrameFinalized callback. This change is necessary in order to allow the PowerPC target code to set the register scavenger frame index after the save-area offset adjustments performed by processFunctionBeforeFrameFinalized. Only after these adjustments have been made is it possible to estimate the size of the stack frame. llvm-svn: 177108
* ArrayRefize some code. No functionality change.Benjamin Kramer2013-03-071-6/+3
| | | | llvm-svn: 176648
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-214-17/+20
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Move MRI liveouts to Sparc return instructions.Jakob Stoklund Olesen2013-02-052-16/+13
| | | | llvm-svn: 174413
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-312-14/+10
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-291-0/+2
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and ↵Eli Bendersky2013-01-231-2/+3
| | | | | | explicitly set this in every target that needs to change it from the default. llvm-svn: 173270
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-072-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. llvm-svn: 171681
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