summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Sparc
Commit message (Collapse)AuthorAgeFilesLines
...
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-013-3/+101
| | | | llvm-svn: 198286
* [SparcV9]: Custom lower UMULO/SMULO so that the arguments are send to ↵Venkatraman Govindaraju2014-01-011-0/+52
| | | | | | __multi3() in correct order. llvm-svn: 198281
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+2
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-293-40/+83
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [SparcV9] For codegen generated library calls that return float, set inreg ↵Venkatraman Govindaraju2013-12-291-0/+6
| | | | | | | | flag manually in LowerCall(). This makes the sparc backend to generate Sparc64 ABI compliant code. llvm-svn: 198149
* [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.Venkatraman Govindaraju2013-12-291-8/+60
| | | | | | Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145
* [Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.Venkatraman Govindaraju2013-12-2611-70/+416
| | | | llvm-svn: 198030
* [Sparc] Add target specific MCExpr class to handle sparc specific modifiers ↵Venkatraman Govindaraju2013-12-263-0/+183
| | | | | | like %hi, %lo, etc., llvm-svn: 198029
* [Sparc] Add MCInstPrinter implementation for SPARC.Venkatraman Govindaraju2013-12-258-4/+188
| | | | llvm-svn: 198028
* Add stack alignment information for Sparc.Rafael Espindola2013-12-191-0/+5
| | | | | | | | | | | | | | | | | This matches the data in clang which was added by Jakob Stoklund Olesen in r179596. Thanks for erikjv on irc for pointing me to the relevant documents: http://sparc.com/standards/64.psabi.1.35.ps.Z page 25: Every stack frame must be 16-byte aligned. http://sparc.com/standards/psABI3rd.pdf page 3-10: Although the architecture requires only word alignment, software convention and the operating system require every stack frame to be doubleword aligned. I tried to add a test, but it looks like sparc doesn't implement dynamic stack realignment. This will be tested in clang shortly. llvm-svn: 197646
* The preferred alignment defaults to the abi alignment. Omit if it is the same.Rafael Espindola2013-12-161-3/+3
| | | | llvm-svn: 197400
* On DataLayout, omit the default of p:64:64:64.Rafael Espindola2013-12-161-4/+2
| | | | llvm-svn: 197397
* Assume defaults to produce smaller datalayout strings.Rafael Espindola2013-12-131-3/+3
| | | | llvm-svn: 197249
* Move Sparc's getDataLayout out of line and add comments.Rafael Espindola2013-12-112-10/+24
| | | | llvm-svn: 196990
* Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi2013-12-111-1/+1
| | | | llvm-svn: 196988
* [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack ↵Venkatraman Govindaraju2013-12-091-3/+5
| | | | | | BIAS on sparcV9. llvm-svn: 196755
* [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that ↵Venkatraman Govindaraju2013-12-092-0/+9
| | | | | | umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
* [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9.Venkatraman Govindaraju2013-12-081-0/+7
| | | | | | This fixes PR18150. llvm-svn: 196735
* Refactor the setting of PrivateGlobalPrefix.Rafael Espindola2013-12-021-2/+0
| | | | | | No functionality change. llvm-svn: 196170
* Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola2013-12-021-0/+7
| | | | llvm-svn: 196065
* [CMake] Let add_public_tablegen_target() provide intrinsics_gen, too.NAKAMURA Takumi2013-11-281-2/+0
| | | | | | | | | | I think, in principle, intrinsics_gen may be added explicitly. That said, it can be added incidentally, since each target already has dependencies to llvm-tblgen. Almost all source files depend on both CommonTaleGen and intrinsics_gen. Explicit add_dependencies() have been pruned under lib/Target. llvm-svn: 195929
* [CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi2013-11-283-5/+1
| | | | | | | | | CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. llvm-svn: 195927
* [CMake] Prune include_directories() in llvm/lib/Target. add_llvm_target() ↵NAKAMURA Takumi2013-11-281-2/+0
| | | | | | sets them. llvm-svn: 195921
* SparcFrameLowering.cpp: Prune 'DL' [-Wunused-variable]NAKAMURA Takumi2013-11-251-1/+0
| | | | llvm-svn: 195590
* [Sparc] Emit large negative adjustments to SP/FP with sethi+xor instead of ↵Venkatraman Govindaraju2013-11-244-40/+108
| | | | | | sethi+or. This generates correct code for both sparc32 and sparc64. llvm-svn: 195576
* [Sparc]: Implement LEA pattern for sparcv9.Venkatraman Govindaraju2013-11-242-4/+11
| | | | llvm-svn: 195575
* [SparcV9]: Do not emit .register directives for global registers that are ↵Venkatraman Govindaraju2013-11-241-1/+1
| | | | | | clobbered by calls but not used in the function itself. llvm-svn: 195574
* [SparcV9] Enable custom lowering of DYNAMIC_STACKALLOC in sparc64.Venkatraman Govindaraju2013-11-241-6/+11
| | | | llvm-svn: 195573
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-192-1/+6
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-182-6/+1
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-152-1/+6
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Expand rotate instructions on sparcv9 as well.Roman Divacky2013-11-121-0/+2
| | | | llvm-svn: 194500
* [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.Venkatraman Govindaraju2013-11-034-28/+184
| | | | llvm-svn: 193957
* [Sparc] Expand FP_TO_UINT, UINT_TO_FP for fp128.Venkatraman Govindaraju2013-11-031-3/+42
| | | | llvm-svn: 193947
* [SparcV9] Add ctpop instruction for i64. Also, expand ctlz, cttz and bswap.Venkatraman Govindaraju2013-11-032-0/+9
| | | | llvm-svn: 193941
* SparcV9 doesnt have rem instruction either.Roman Divacky2013-10-311-0/+8
| | | | llvm-svn: 193789
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-291-1/+1
| | | | llvm-svn: 193627
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-4/+2
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. llvm-svn: 192760
* [Sparc] Disable tail call optimization for sparc64.Venkatraman Govindaraju2013-10-091-0/+3
| | | | | | This patch fixes PR17506. llvm-svn: 192294
* SparcJITInfo.cpp: Prune "default:" label to fix a warning. ↵NAKAMURA Takumi2013-10-081-1/+0
| | | | | | [-Wcovered-switch-default] llvm-svn: 192179
* Prune trailing linefeeds.NAKAMURA Takumi2013-10-081-2/+0
| | | | llvm-svn: 192178
* [Sparc] Implement JIT for SPARC.Venkatraman Govindaraju2013-10-0812-44/+586
| | | | | | | No new testcases. However, this patch makes all supported JIT testcases in test/ExecutionEngine pass on Sparc. llvm-svn: 192176
* [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use ↵Venkatraman Govindaraju2013-10-082-3/+4
| | | | | | DelaySlotFiller to fill the delay slot instead. llvm-svn: 192160
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-11/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-7/+22
| | | | llvm-svn: 192056
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-062-7/+55
| | | | | | This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. llvm-svn: 192054
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-4/+4
| | | | | | addx/subx does not modify conditional codes whereas addxcc/subxx does. llvm-svn: 192053
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-4/+13
| | | | llvm-svn: 192023
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP ↵Venkatraman Govindaraju2013-10-051-1/+1
| | | | | | with fp128 operand. llvm-svn: 192015
* [Sparc] Correct the floating point conditional code mapping in ↵Venkatraman Govindaraju2013-10-041-8/+8
| | | | | | GetOppositeBranchCondition(). llvm-svn: 192006
OpenPOWER on IntegriCloud