summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Sparc
Commit message (Collapse)AuthorAgeFilesLines
* This method has now been changed to preserve flags for us!Chris Lattner2003-08-051-5/+2
| | | | llvm-svn: 7603
* * Removed `using' declaration, now use full namespace qualifier std::stringMisha Brukman2003-08-051-43/+43
| | | | | | * Simplified code by using an inline function instead of copy-pasted code llvm-svn: 7597
* * Set annul bit to be 0, because the Sparc backend currently does not use it.Misha Brukman2003-08-051-5/+5
| | | | | | | * Use the name of the predict field instead of just the const 1 in the Instruction. llvm-svn: 7592
* Transition to using 'let X = y' instead of 'set X = y'.Chris Lattner2003-08-045-220/+220
| | | | llvm-svn: 7565
* DEBUG got moved to Debug.hChris Lattner2003-08-011-2/+3
| | | | llvm-svn: 7495
* Remove makefile complexity by always running tablegen with its final outputChris Lattner2003-08-011-7/+2
| | | | | | directory. llvm-svn: 7485
* Add all arithmetic operators to ConstantExprToString().Vikram S. Adve2003-08-011-0/+40
| | | | | | | | Note that some generated operators (like &, | or ^) may not be supported by the assembler -- but if they've got this far, it's better to generate them and let the assembler decide. llvm-svn: 7476
* *Both* operands of divide need sign-extension before divide (if smallerVikram S. Adve2003-08-011-8/+16
| | | | | | than machine register size), not just the second operand. llvm-svn: 7475
* Put back the separate pass to decompose multi-dimensional referencesVikram S. Adve2003-08-011-0/+3
| | | | | | | | since it is *necessary* for correct code generation. Only optional transformations belong in the PreOpts pass (which needs to be renamed from PreSelection to PreOpts). llvm-svn: 7474
* We no longer need to preprocess SparcV9.td before sending it through tablegenChris Lattner2003-07-302-30/+30
| | | | llvm-svn: 7437
* When emitting a constant, check for ConstantExpr beforeVikram S. Adve2003-07-301-14/+15
| | | | | | ordinary (primitive) types since ConstantExprs may be of primitive type! llvm-svn: 7418
* Conform to the new interface for describing target registers... even thoughChris Lattner2003-07-301-14/+24
| | | | | | it's currently not used. llvm-svn: 7416
* Only regenerate the .inc file if IT has changed, not just if the .td filesChris Lattner2003-07-301-4/+13
| | | | | | have changed. llvm-svn: 7414
* Do not use 'cpp' directlyChris Lattner2003-07-291-1/+1
| | | | llvm-svn: 7404
* * Cleaned up and corrected comments wrt instruction formatsMisha Brukman2003-07-291-18/+18
| | | | | | * Enabled STXFSR instructions llvm-svn: 7400
* Make emitFarCall() public, and add a few comments to functions.Misha Brukman2003-07-291-3/+27
| | | | llvm-svn: 7399
* Unify all constant evaluations that depend on register sizeVikram S. Adve2003-07-292-72/+104
| | | | | | in ConvertConstantToIntType. llvm-svn: 7395
* Rename 'dump-asm' to 'dump-input' and really print it just before code-gen.Vikram S. Adve2003-07-291-6/+6
| | | | llvm-svn: 7394
* Bug fix: don't unnecessarily pretty-print control-characters, some ofVikram S. Adve2003-07-291-15/+4
| | | | | | which were wrong (particularly, '\a' for '\007'). llvm-svn: 7393
* Add ConvertConstantToIntType() to unify all constant handlingVikram S. Adve2003-07-291-50/+16
| | | | | | | | | that depends on machine register size. Moved insertCallerSavingCode() to PhyRegAlloc and moved isRegVolatile and modifiedByCall to TargetRegInfo: they are all machine independent. Remove several dead functions. llvm-svn: 7392
* Add code to support stack spill/temp offsets that don't fit in theVikram S. Adve2003-07-291-238/+99
| | | | | | | immed. field. Moved insertCallerSavingCode() to PhyRegAlloc: it is now machine independent. Remove all uses of PhyRegAlloc. llvm-svn: 7391
* * Correctly emit a far call if the target address does not fit into 30 bitsMisha Brukman2003-07-291-17/+15
| | | | | | | instead of assert()ing * Fixed a nasty bug where '07' was used instead of register 'o7' llvm-svn: 7382
* Specify the value type for the register, not just the size.Chris Lattner2003-07-281-1/+4
| | | | llvm-svn: 7357
* This code doesn't modify the LLVM structure, keep stuff constChris Lattner2003-07-263-6/+6
| | | | llvm-svn: 7343
* (1) Major fix to the way unused regs. are marked and found for the FPVikram S. Adve2003-07-254-566/+140
| | | | | | | | | | | | | Single and FP double reg types (which share the same reg class). Now all methods marking/finding unused regs consider the regType within the reg class, and SparcFloatRegClass specializes this code. (2) Remove machine-specific regalloc. methods that are no longer needed. In particular, arguments and return value from a call do not need machine-specific code for allocation. (3) Rename TargetRegInfo::getRegType variants to avoid unintentional overloading when an include file is omitted. llvm-svn: 7334
* 1. Fix a case that was marking the invalid reg. num. (-1) as used,Vikram S. Adve2003-07-251-14/+35
| | | | | | | | causing a nasty array bound error later. 2. Fix silly typo causing logical shift of unsigned long to use SRL instead of SRLX. llvm-svn: 7330
* Remove redundant const qualifiers from cast<> expressionsChris Lattner2003-07-231-1/+1
| | | | llvm-svn: 7253
* Simplify code by using ConstantInt::getRawValue instead of checking to seeChris Lattner2003-07-232-14/+6
| | | | | | whether the constant is signed or unsigned, then casting llvm-svn: 7252
* Simplify code a bitChris Lattner2003-07-211-9/+9
| | | | llvm-svn: 7217
* Added special consideration for instrumentation strategyAnand Shukla2003-07-203-0/+24
| | | | llvm-svn: 7208
* Fixed the number translation scheme for the integer condition code registers: itMisha Brukman2003-07-162-32/+8
| | | | | | | | | | now works in instructions which require a 2-bit or 3-bit INTcc code. Incidentally, that means that the representation of INTcc registers is now the same in both integer and FP instructions. Thus, code became much simpler and cleaner. llvm-svn: 7185
* The name should really be `simm11' to follow the naming convention, but this hasMisha Brukman2003-07-161-2/+2
| | | | | | no change in functionality. llvm-svn: 7184
* No need for a second immediate field if the class already inherits one.Misha Brukman2003-07-151-2/+1
| | | | llvm-svn: 7182
* Encode predict = 1 by default, because the Sparc assembler does this.Misha Brukman2003-07-151-4/+4
| | | | llvm-svn: 7181
* Correctly handle calls to functions which are further away than 2**32 bits willMisha Brukman2003-07-152-6/+97
| | | | | | | | | | | | allow, i.e. make a sequence of instructions to enable an indirect call using jump-and-link and 2 temporary registers (which we save and ultimately restore). Warning: if the delay slot of a function call is used to do meaningful work and not just a NOP, this behavior is incorrect. However, the Sparc backend does not yet utilize the delay slots effectively, so it is not necessary to make an overly complicated algorithm for something that's not used. llvm-svn: 7178
* * Added support for the %ccr registerMisha Brukman2003-07-142-77/+24
| | | | | | | | * FP double registers are now coded correctly * Removed function which converted registers based on register types, it was broken (because regTypes are broken) llvm-svn: 7175
* The word `separate' only has one `e'.Misha Brukman2003-07-141-1/+1
| | | | llvm-svn: 7173
* Several important bug fixes:Vikram S. Adve2003-07-101-160/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops. (2) Conditional move instructions must distinguish signed and unsigned condition codes, e.g., MOVLE vs. MOVLEU. (3) Conditional-move-on-register was using the cond-move-on-cc opcodes, which produces a valid-looking instruction with bogus registers! (4) Here's a really cute one: dividing-by-2^k for negative numbers needs to add 2^k-1 before shifting, not add 1 after shifting. Sadly, these are the same when k=0 so our poor test case worked fine. (5) Casting between signed and unsigned values was not correct: completely reimplemented. (6) Zero-extension on unsigned values was bogus: I was only doing the SRL and not the SLLX before it. Don't know WHAT I was thinking! (7) And the most important class of changes: Sign-extensions on signed values. Signed values are not sign-extended after ordinary operations, so they must be sign-extended before the following cases: -- passing to an external or unknown function -- returning from a function -- using as operand 2 of DIV or REM -- using as either operand of condition-code setting operation (currently only SUBCC), with smaller than 32-bit operands Also, a couple of improvements: (1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also. (2) Convert SetCC-Const into a conditional-move-on-register (case 41) if the constant is 0. This was only being done for branch-on-SetCC-Const when the branch is folded with the SetCC-Const. llvm-svn: 7159
* Bug fix in creating constants: need 1U << 31, not 1 << 31.Vikram S. Adve2003-07-101-1/+1
| | | | llvm-svn: 7158
* Fold cast-to-bool into not. Later, this should also be folded into otherVikram S. Adve2003-07-101-0/+1
| | | | | | boolean operations: AND, OR, XOR. llvm-svn: 7157
* Several fixes to handling of int CC register:Vikram S. Adve2003-07-103-179/+48
| | | | | | | | | | | | | | | | | | | | (1) An int CC live range must be spilled if there are any interferences, even if no other "neighbour" in the interf. graph has been allocated that reg. yet. This is actually true of any class with only one reg! (2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must be spilled so that the machine-independent spill code doesn't have to make the machine-dependent decision of which CC name to use based on operand type: %xcc or %icc. (These are two halves of the same register.) (3) LR->isMarkedForSpill() is no longer the same as LR->hasColor(). These should never have been the same, and this is necessary now for #2. (4) All RDCCR and WRCCR instructions are directly generated with the phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to deal with this. llvm-svn: 7151
* Elaborated assembly syntax of instructions in the comments.Misha Brukman2003-07-071-65/+64
| | | | llvm-svn: 7120
* Removed unnecessary assignment (it was taken care by a superclass) and clarifiedMisha Brukman2003-07-071-6/+5
| | | | | | some comments. llvm-svn: 7119
* Moved RegClassIDs enum to be next to the RegTypes enum.Misha Brukman2003-07-071-14/+14
| | | | llvm-svn: 7114
* Correction to last fix: Pointer types do not return true in Type::IsIntegral().Vikram S. Adve2003-07-061-6/+9
| | | | llvm-svn: 7113
* Major bug fix though it happened rarely (only on a compare after anVikram S. Adve2003-07-065-37/+82
| | | | | | | | integer overflow): We need to use %icc and not %xcc for comparisons on 32-bit or smaller integer values. llvm-svn: 7111
* Make the RegClassID values public -- there is no other way to get them.Vikram S. Adve2003-07-061-4/+6
| | | | llvm-svn: 7109
* Apparently, the "regType" and "regClass" used in the Sparc backend are not bothMisha Brukman2003-07-032-42/+95
| | | | | | | | | | | correct: empirically, "regType" is wrong for a number of registers. Thus, one can only rely on the "regClass" to figure out what kind of register one is dealing with. This change switches to using only "regClass" and adds a few extra DEBUG() print statements and a few clean-ups in comments and code, mostly minor. llvm-svn: 7103
* * Force all "don't care" bits to 0 so that there are absolutely no unset bits inMisha Brukman2003-07-022-14/+18
| | | | | | | | the TableGen descriptions; all unset bits are thus errors. * As a result, found and fixed instructions where some operands were not actually assigned into the right portion of the instruction. llvm-svn: 7074
* The classes F4_3 and F4_4 have an `rd' operand that needs to be set.Misha Brukman2003-07-021-0/+3
| | | | llvm-svn: 7073
OpenPOWER on IntegriCloud