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* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-123-4/+85
| | | | llvm-svn: 123310
* Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to Venkatraman Govindaraju2011-01-122-3/+5
| | | | | | ensure %o7 is not assigned as the destination of getpcx instruction. llvm-svn: 123304
* Fix SPARC backend call instruction so that arguments passed through registersVenkatraman Govindaraju2011-01-122-11/+24
| | | | | | | are correctly marked as used instead of passing all possible argument registers as used. llvm-svn: 123301
* SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CCVenkatraman Govindaraju2011-01-111-15/+19
| | | | llvm-svn: 123281
* Update CMake stuffAnton Korobeynikov2011-01-101-1/+1
| | | | llvm-svn: 123171
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-104-15/+17
| | | | | | and fixes here and there. llvm-svn: 123170
* SPARC backend fix: correctly passing arguments through stackVenkatraman Govindaraju2010-12-291-23/+51
| | | | llvm-svn: 122626
* Multiple SPARC backend fixes: added Y register; updated select_cc, subx, ↵Venkatraman Govindaraju2010-12-283-21/+35
| | | | | | | | subxcc defs/uses; and fixed CustomInserter. llvm-svn: 122607
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-10/+10
| | | | llvm-svn: 122513
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-212-7/+7
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-19/+19
| | | | llvm-svn: 119990
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-183-6/+2
| | | | llvm-svn: 119740
* Attempt to unbreak cmake-based buildsAnton Korobeynikov2010-11-151-0/+1
| | | | llvm-svn: 119098
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-156-62/+130
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place llvm-svn: 119097
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-145-22/+2
| | | | | | | that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. llvm-svn: 119056
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-1/+1
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-8/+6
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-7/+8
| | | | llvm-svn: 114461
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-211-1/+1
| | | | | | SelectionDAG::getExtLoad overload, and eliminate it. llvm-svn: 114446
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-211-14/+16
| | | | llvm-svn: 114410
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-7/+4
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* Don't call Predicate_* methods directly from Sparc target.Jakob Stoklund Olesen2010-08-172-14/+6
| | | | | | | | | Modernize predicates a bit. The Predicate_* methods are not used by TableGen any longer. They are only emitted for the sake of legacy code. llvm-svn: 111263
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-171-1/+1
| | | | llvm-svn: 111241
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-062-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-062-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-052-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-46/+0
| | | | llvm-svn: 108567
* Don't pass StringRef by reference.Benjamin Kramer2010-07-142-4/+4
| | | | llvm-svn: 108366
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-67/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for Sparc.Jakob Stoklund Olesen2010-07-112-28/+18
| | | | llvm-svn: 108086
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-071-1/+1
| | | | | | for consistency sake. llvm-svn: 107820
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-5/+9
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-2/+2
| | | | llvm-svn: 107710
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-14/+13
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Revert r107655.Dan Gohman2010-07-061-13/+14
| | | | llvm-svn: 107668
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-14/+13
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-5/+5
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove isTwoAddress from Sparc.Eric Christopher2010-06-211-1/+1
| | | | llvm-svn: 106466
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-3/+3
| | | | llvm-svn: 106279
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-5/+5
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* cleanupRafael Espindola2010-06-022-10/+0
| | | | llvm-svn: 105322
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-0/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-6/+0
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-0/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-114-4/+12
| | | | | | | | Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-062-5/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-062-4/+8
| | | | llvm-svn: 103193
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-012-9/+5
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Delete an unnecessary reference to SelectionDAGISel::BB.Dan Gohman2010-04-191-1/+0
| | | | llvm-svn: 101824
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