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* (1) Major fix to the way unused regs. are marked and found for the FPVikram S. Adve2003-07-254-566/+140
| | | | | | | | | | | | | Single and FP double reg types (which share the same reg class). Now all methods marking/finding unused regs consider the regType within the reg class, and SparcFloatRegClass specializes this code. (2) Remove machine-specific regalloc. methods that are no longer needed. In particular, arguments and return value from a call do not need machine-specific code for allocation. (3) Rename TargetRegInfo::getRegType variants to avoid unintentional overloading when an include file is omitted. llvm-svn: 7334
* 1. Fix a case that was marking the invalid reg. num. (-1) as used,Vikram S. Adve2003-07-251-14/+35
| | | | | | | | causing a nasty array bound error later. 2. Fix silly typo causing logical shift of unsigned long to use SRL instead of SRLX. llvm-svn: 7330
* Remove redundant const qualifiers from cast<> expressionsChris Lattner2003-07-231-1/+1
| | | | llvm-svn: 7253
* Simplify code by using ConstantInt::getRawValue instead of checking to seeChris Lattner2003-07-232-14/+6
| | | | | | whether the constant is signed or unsigned, then casting llvm-svn: 7252
* Simplify code a bitChris Lattner2003-07-211-9/+9
| | | | llvm-svn: 7217
* Added special consideration for instrumentation strategyAnand Shukla2003-07-203-0/+24
| | | | llvm-svn: 7208
* Fixed the number translation scheme for the integer condition code registers: itMisha Brukman2003-07-162-32/+8
| | | | | | | | | | now works in instructions which require a 2-bit or 3-bit INTcc code. Incidentally, that means that the representation of INTcc registers is now the same in both integer and FP instructions. Thus, code became much simpler and cleaner. llvm-svn: 7185
* The name should really be `simm11' to follow the naming convention, but this hasMisha Brukman2003-07-161-2/+2
| | | | | | no change in functionality. llvm-svn: 7184
* No need for a second immediate field if the class already inherits one.Misha Brukman2003-07-151-2/+1
| | | | llvm-svn: 7182
* Encode predict = 1 by default, because the Sparc assembler does this.Misha Brukman2003-07-151-4/+4
| | | | llvm-svn: 7181
* Correctly handle calls to functions which are further away than 2**32 bits willMisha Brukman2003-07-152-6/+97
| | | | | | | | | | | | allow, i.e. make a sequence of instructions to enable an indirect call using jump-and-link and 2 temporary registers (which we save and ultimately restore). Warning: if the delay slot of a function call is used to do meaningful work and not just a NOP, this behavior is incorrect. However, the Sparc backend does not yet utilize the delay slots effectively, so it is not necessary to make an overly complicated algorithm for something that's not used. llvm-svn: 7178
* * Added support for the %ccr registerMisha Brukman2003-07-142-77/+24
| | | | | | | | * FP double registers are now coded correctly * Removed function which converted registers based on register types, it was broken (because regTypes are broken) llvm-svn: 7175
* The word `separate' only has one `e'.Misha Brukman2003-07-141-1/+1
| | | | llvm-svn: 7173
* Several important bug fixes:Vikram S. Adve2003-07-101-160/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops. (2) Conditional move instructions must distinguish signed and unsigned condition codes, e.g., MOVLE vs. MOVLEU. (3) Conditional-move-on-register was using the cond-move-on-cc opcodes, which produces a valid-looking instruction with bogus registers! (4) Here's a really cute one: dividing-by-2^k for negative numbers needs to add 2^k-1 before shifting, not add 1 after shifting. Sadly, these are the same when k=0 so our poor test case worked fine. (5) Casting between signed and unsigned values was not correct: completely reimplemented. (6) Zero-extension on unsigned values was bogus: I was only doing the SRL and not the SLLX before it. Don't know WHAT I was thinking! (7) And the most important class of changes: Sign-extensions on signed values. Signed values are not sign-extended after ordinary operations, so they must be sign-extended before the following cases: -- passing to an external or unknown function -- returning from a function -- using as operand 2 of DIV or REM -- using as either operand of condition-code setting operation (currently only SUBCC), with smaller than 32-bit operands Also, a couple of improvements: (1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also. (2) Convert SetCC-Const into a conditional-move-on-register (case 41) if the constant is 0. This was only being done for branch-on-SetCC-Const when the branch is folded with the SetCC-Const. llvm-svn: 7159
* Bug fix in creating constants: need 1U << 31, not 1 << 31.Vikram S. Adve2003-07-101-1/+1
| | | | llvm-svn: 7158
* Fold cast-to-bool into not. Later, this should also be folded into otherVikram S. Adve2003-07-101-0/+1
| | | | | | boolean operations: AND, OR, XOR. llvm-svn: 7157
* Several fixes to handling of int CC register:Vikram S. Adve2003-07-103-179/+48
| | | | | | | | | | | | | | | | | | | | (1) An int CC live range must be spilled if there are any interferences, even if no other "neighbour" in the interf. graph has been allocated that reg. yet. This is actually true of any class with only one reg! (2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must be spilled so that the machine-independent spill code doesn't have to make the machine-dependent decision of which CC name to use based on operand type: %xcc or %icc. (These are two halves of the same register.) (3) LR->isMarkedForSpill() is no longer the same as LR->hasColor(). These should never have been the same, and this is necessary now for #2. (4) All RDCCR and WRCCR instructions are directly generated with the phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to deal with this. llvm-svn: 7151
* Elaborated assembly syntax of instructions in the comments.Misha Brukman2003-07-071-65/+64
| | | | llvm-svn: 7120
* Removed unnecessary assignment (it was taken care by a superclass) and clarifiedMisha Brukman2003-07-071-6/+5
| | | | | | some comments. llvm-svn: 7119
* Moved RegClassIDs enum to be next to the RegTypes enum.Misha Brukman2003-07-071-14/+14
| | | | llvm-svn: 7114
* Correction to last fix: Pointer types do not return true in Type::IsIntegral().Vikram S. Adve2003-07-061-6/+9
| | | | llvm-svn: 7113
* Major bug fix though it happened rarely (only on a compare after anVikram S. Adve2003-07-065-37/+82
| | | | | | | | integer overflow): We need to use %icc and not %xcc for comparisons on 32-bit or smaller integer values. llvm-svn: 7111
* Make the RegClassID values public -- there is no other way to get them.Vikram S. Adve2003-07-061-4/+6
| | | | llvm-svn: 7109
* Apparently, the "regType" and "regClass" used in the Sparc backend are not bothMisha Brukman2003-07-032-42/+95
| | | | | | | | | | | correct: empirically, "regType" is wrong for a number of registers. Thus, one can only rely on the "regClass" to figure out what kind of register one is dealing with. This change switches to using only "regClass" and adds a few extra DEBUG() print statements and a few clean-ups in comments and code, mostly minor. llvm-svn: 7103
* * Force all "don't care" bits to 0 so that there are absolutely no unset bits inMisha Brukman2003-07-022-14/+18
| | | | | | | | the TableGen descriptions; all unset bits are thus errors. * As a result, found and fixed instructions where some operands were not actually assigned into the right portion of the instruction. llvm-svn: 7074
* The classes F4_3 and F4_4 have an `rd' operand that needs to be set.Misha Brukman2003-07-021-0/+3
| | | | llvm-svn: 7073
* Properly fix instruction syntax in comments, using `imm' for instructions thatMisha Brukman2003-07-021-34/+34
| | | | | | use an immediate value instead of a register. llvm-svn: 7072
* Fixed instruction syntax in the comments (specifies how instr is used).Misha Brukman2003-07-021-83/+83
| | | | llvm-svn: 7071
* Force fixed-size but large alloca objects to the dynamically allocatedVikram S. Adve2003-07-021-8/+14
| | | | | | | | area to avoid using up precious stack space within the 4095 offset limit from %fp. Such objects that would themselves live at a large offset were being put there already so this is a simple change. llvm-svn: 7066
* (1) Major bug fix: DecomposeArrayRef() replaces its argument instr. andVikram S. Adve2003-07-021-45/+22
| | | | | | | | | | | | deletes it, but we were merrily trying to fix the operands of that instruction anyway! Instead, fix the replacement instruction. (2) An Improvement: Check for and extract global values in all operands, not just in known pointer operands. For example, they can occur in call arguments, and probably other unforeseeable places as well. This also eliminates the special-case handling of Load and Store. llvm-svn: 7053
* Bug/case fixes:Vikram S. Adve2003-07-022-12/+25
| | | | | | | | | | | | (1) select: Ok to convert a pointer to a float or double. (2) regalloc: Some MachineInstr* for caller-saving code before a call were being inserted before and after the call! (3) Don't insert the caller-saving instructions in the MachineCodeForInstruction for the Call instruction. *All* instructions generated by register allocation need to be recorded in those maps, but it needs to be done uniformly. llvm-svn: 7051
* Merged in autoconf branch. This provides configuration via the autoconfJohn Criswell2003-06-303-9/+18
| | | | | | system. llvm-svn: 7014
* Add the padding needed for variable-size alloca's, which should work now.Vikram S. Adve2003-06-231-6/+14
| | | | llvm-svn: 6859
* Some preprocessors doen't support // comments and get confusedChris Lattner2003-06-201-1/+1
| | | | llvm-svn: 6821
* RDCCR defines arg. #1, not arg. #2.Vikram S. Adve2003-06-201-1/+1
| | | | llvm-svn: 6796
* lib/Target/Sparc/Sparc.cpp:Brian Gaeke2003-06-181-1/+22
| | | | | | | | | | | | | | | | | | | | | Move LowerAllocations, PrintFunction, and SymbolStripping passes, and the corresponding -disable-strip and -d options, over here to the SPARC target-specific bits of llc. Rename -d to -dump-asm. tools/llc/Makefile: Reindent. Add x86 library so that llc compiles again. tools/llc/llc.cpp: Remove support for running arbitrary optimization passes. Use opt instead. Remove LowerAllocations, PrintFunction, and SymbolStripping passes, as noted above. Allow user to select a backend (x86 or SPARC); default to guessing from the endianness/pointer size of the input bytecode file. Fix typos. Delete empty .s file and exit with error status if target does not support static compilation. llvm-svn: 6776
* These instructions really take three operands. This fixes some assertionsChris Lattner2003-06-181-2/+2
| | | | llvm-svn: 6765
* Rename FInfo.cpp to FunctionInfo.cpp, eliminate FInfo.hChris Lattner2003-06-161-2/+0
| | | | llvm-svn: 6712
* move contents of include/llvm/Reoptimizer/Mapping/FInfo.h into here, it is ↵Chris Lattner2003-06-161-0/+2
| | | | | | sparc internal llvm-svn: 6711
* Fix invalid number of arguments problemChris Lattner2003-06-161-2/+2
| | | | llvm-svn: 6692
* Updated for the new projects Makefile.John Criswell2003-06-111-4/+4
| | | | llvm-svn: 6678
* Print address out as hex.Misha Brukman2003-06-061-1/+1
| | | | llvm-svn: 6657
* Added 'r' and 'i' versions to WRCCR.Misha Brukman2003-06-061-1/+2
| | | | llvm-svn: 6656
* * Changed Bcc instructions to behave like BPcc instructionsMisha Brukman2003-06-067-38/+64
| | | | | | | | | * BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes llvm-svn: 6655
* * Removed PreSelection pass because that is now done in the JITMisha Brukman2003-06-061-22/+10
| | | | | | | * Removed instruction scheduling as it is too slow to run in a JIT environment * Removed other passes because they aren't necessary and can slow JIT down llvm-svn: 6652
* Fixed a bunch of test cases in test/Regression/Jello which could not get theMisha Brukman2003-06-061-2/+13
| | | | | | address of a floating-point (allocated via ConstantPool) correctly. llvm-svn: 6647
* * If a global is not a function, just ask the MachineCodeEmitter for the addrMisha Brukman2003-06-061-3/+3
| | | | | | * Do not block a print statement with a DEBUG() guard if we're going to abort() llvm-svn: 6645
* The SUB*i instructions belong to a different class than their SUB*r brethren.Misha Brukman2003-06-061-4/+4
| | | | llvm-svn: 6644
* Put all debug print statements under the DEBUG() guard to make output clean soMisha Brukman2003-06-061-35/+36
| | | | | | that tests can automatically diff the output. llvm-svn: 6642
* Fixed confusion between register classes and register types.Misha Brukman2003-06-051-2/+4
| | | | | | Now %fcc registers are recognized correctly. llvm-svn: 6640
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