| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 7217
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llvm-svn: 7208
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(1) An int CC live range must be spilled if there are any interferences,
even if no other "neighbour" in the interf. graph has been allocated
that reg. yet. This is actually true of any class with only one reg!
(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
be spilled so that the machine-independent spill code doesn't have to
make the machine-dependent decision of which CC name to use based on
operand type: %xcc or %icc. (These are two halves of the same register.)
(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
These should never have been the same, and this is necessary now for #2.
(4) All RDCCR and WRCCR instructions are directly generated with the
phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
deal with this.
llvm-svn: 7151
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integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.
llvm-svn: 7111
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(1) select: Ok to convert a pointer to a float or double.
(2) regalloc: Some MachineInstr* for caller-saving code before a call
were being inserted before and after the call!
(3) Don't insert the caller-saving instructions in the
MachineCodeForInstruction for the Call instruction.
*All* instructions generated by register allocation need to be
recorded in those maps, but it needs to be done uniformly.
llvm-svn: 7051
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llvm-svn: 6692
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* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
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llvm-svn: 6503
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call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.
llvm-svn: 6465
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llvm-svn: 6377
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Fixed spilling of %fcc[0-3] which are part of %fsr.
Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
llvm-svn: 6339
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Eliminated `using' directives.
llvm-svn: 6261
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llvm-svn: 6249
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llvm-svn: 6145
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llvm-svn: 5316
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Eliminate dependency on RegClass.h
llvm-svn: 5315
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llvm-svn: 5307
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llvm-svn: 5305
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llvm-svn: 5303
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llvm-svn: 5291
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llvm/CodeGen/FunctionLiveVarInfo.h
llvm-svn: 5284
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llvm-svn: 5204
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* Constant pool and frame info is no longer directly in MachineFunction
llvm-svn: 5177
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llvm-svn: 4408
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llvm-svn: 4354
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llvm-svn: 4347
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llvm-svn: 4345
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MachineOperand::getType()
llvm-svn: 4331
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llvm-svn: 4301
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overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
bitvector. Sped up LLC a little less than 10% in a debug build!
llvm-svn: 4261
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llvm-svn: 4170
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llvm-svn: 4128
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created here. Instead they are created in LiveRangeInfo.cpp. This
simplifies the code here quite a bit.
llvm-svn: 3965
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- Added new method Type::isIntegral() that is the same as isInteger, but
also accepts bool.
llvm-svn: 3574
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- Eliminate Sparc*Order classes, moving contents to Sparc*Class classes
- get register name methods now return const char * const pointers instead
of std::string's.
- Added file header comments to SparcRegClassInfo.(cpp|h)
- Moved BIG constant arrays out of SparcRegClassInfo.h, into
SparcRegInfo.cpp. This should allow a LOT of std::string constructors to
not have to be called.
llvm-svn: 3295
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directory is built.
llvm-svn: 3073
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llvm-svn: 3056
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-- FP argument to a function with no prototype going on stack
was not being copied to the stack in colorCallArgs().
-- Put caller-saving code *before* argument copying code so that
we don't trash a register before saving it!
-- Two other minor fixes.
llvm-svn: 2855
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llvm-svn: 2845
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handle conditional move instructions:
-- cpMem<->Reg functions now support CC registers (int and FP) correctly.
Also, cpMem<->Reg functions now return a vector of machine instructions.
-- Scratch registers must be explicitly provided to cpMem<->Reg when
needed, since CC regs need one to be copied to/from memory.
-- CC regs are saved to a scratch register instead of stack.
-- All regs used by a instruction are now recorded in MachineInstr::regsUsed,
since regs used to save values *across* an instruction are not obvious
either from the operands or from the LiveVar sets.
-- An (explicit or implicit) operand may now be both a def and a use.
This is needed for conditional move operations.
So an operand may need spill code both before and after the instruction.
Other changes:
-- Added several get{Class,Type} functions.
-- Added unified-to-local register number conversion.
-- class MachineCodeForBasicBlock is now an annotation on BasicBlock.
-- Suggest/Color methods may modify the MachineInstr (and always did),
so don't make that argument const!
-- Caller-saving code doesn't need its special purpose code for
handling CC registers since cpMem<->Reg handle those correctly now.
llvm-svn: 2834
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llvm-svn: 2791
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For details, See: docs/2002-06-25-MegaPatchInfo.txt
llvm-svn: 2778
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llvm-svn: 2756
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-- correct sign extensions for integer casts and for shift-by-constant
instructions generated for integer multiply
-- passing FP arguments to functions with more than 6 arguments
-- passing FP arguments to varargs functions
-- passing FP arguments to functions with no prototypes
-- incorrect stack frame size when padding a section
-- folding getelementptr operations with mixed array and struct indexes
-- use uint64_t instead of uint for constant offsets in mem operands
-- incorrect coloring for CC registers (both int and FP): interferences
were being completely ignored for int CC and were considered but no
spills were marked for fp CC!
Also some code improvements:
-- better interface to generating machine instr for common cases
(many places still need to be updated to use this interface)
-- annotations on MachineInstr to communicate information from
one codegen phase to another (now used to pass information about
CALL/JMPLCALL operands from selection to register allocation)
-- all sizes and offests in class TargetData are uint64_t instead of uint
llvm-svn: 2640
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llvm-svn: 2397
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llvm-svn: 2336
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llvm-svn: 2322
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function calls were simply wrong; other functions were just not
using all available registers.
llvm-svn: 2316
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llvm-svn: 2254
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llvm-svn: 2215
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