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* *Both* operands of divide need sign-extension before divide (if smallerVikram S. Adve2003-08-011-8/+16
| | | | | | than machine register size), not just the second operand. llvm-svn: 7475
* Unify all constant evaluations that depend on register sizeVikram S. Adve2003-07-291-6/+12
| | | | | | in ConvertConstantToIntType. llvm-svn: 7395
* 1. Fix a case that was marking the invalid reg. num. (-1) as used,Vikram S. Adve2003-07-251-14/+35
| | | | | | | | causing a nasty array bound error later. 2. Fix silly typo causing logical shift of unsigned long to use SRL instead of SRLX. llvm-svn: 7330
* Several important bug fixes:Vikram S. Adve2003-07-101-160/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops. (2) Conditional move instructions must distinguish signed and unsigned condition codes, e.g., MOVLE vs. MOVLEU. (3) Conditional-move-on-register was using the cond-move-on-cc opcodes, which produces a valid-looking instruction with bogus registers! (4) Here's a really cute one: dividing-by-2^k for negative numbers needs to add 2^k-1 before shifting, not add 1 after shifting. Sadly, these are the same when k=0 so our poor test case worked fine. (5) Casting between signed and unsigned values was not correct: completely reimplemented. (6) Zero-extension on unsigned values was bogus: I was only doing the SRL and not the SLLX before it. Don't know WHAT I was thinking! (7) And the most important class of changes: Sign-extensions on signed values. Signed values are not sign-extended after ordinary operations, so they must be sign-extended before the following cases: -- passing to an external or unknown function -- returning from a function -- using as operand 2 of DIV or REM -- using as either operand of condition-code setting operation (currently only SUBCC), with smaller than 32-bit operands Also, a couple of improvements: (1) Fold cast-to-bool into Not(bool). Need to do this for And, Or, XOR also. (2) Convert SetCC-Const into a conditional-move-on-register (case 41) if the constant is 0. This was only being done for branch-on-SetCC-Const when the branch is folded with the SetCC-Const. llvm-svn: 7159
* Major bug fix though it happened rarely (only on a compare after anVikram S. Adve2003-07-061-9/+7
| | | | | | | | integer overflow): We need to use %icc and not %xcc for comparisons on 32-bit or smaller integer values. llvm-svn: 7111
* Force fixed-size but large alloca objects to the dynamically allocatedVikram S. Adve2003-07-021-8/+14
| | | | | | | | area to avoid using up precious stack space within the 4095 offset limit from %fp. Such objects that would themselves live at a large offset were being put there already so this is a simple change. llvm-svn: 7066
* Bug/case fixes:Vikram S. Adve2003-07-021-2/+3
| | | | | | | | | | | | (1) select: Ok to convert a pointer to a float or double. (2) regalloc: Some MachineInstr* for caller-saving code before a call were being inserted before and after the call! (3) Don't insert the caller-saving instructions in the MachineCodeForInstruction for the Call instruction. *All* instructions generated by register allocation need to be recorded in those maps, but it needs to be done uniformly. llvm-svn: 7051
* Add the padding needed for variable-size alloca's, which should work now.Vikram S. Adve2003-06-231-6/+14
| | | | llvm-svn: 6859
* * Changed Bcc instructions to behave like BPcc instructionsMisha Brukman2003-06-061-9/+9
| | | | | | | | | * BPA and BPN do not take a %cc register as a parameter * SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions * Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit * Added WRCCR{r,i} opcodes llvm-svn: 6655
* * Convert load/store opcodes from register to immediate forms.Misha Brukman2003-06-031-9/+11
| | | | | | * Stop code from wrapping to the next line. llvm-svn: 6566
* SparcInstr.def: added 'r' and 'i' versions of MOV(F)cc instructionsMisha Brukman2003-06-021-16/+30
| | | | | | | | | | | | | | | SparcInstrSelection.cpp: * Fixed opcodes to return correct 'i' version since the two functions are each only used in one place. * Changed name of function to have an 'i' in the name to signify that they each return an immediate form of the opcode. * Added a warning if either of the functions is ever used in a context which requires a register-version opcode. SparcV9_F4.td: fixed class F4_3, added F4_4 and notes that F4_{1,2} need fixing SparcV9.td: added the MOV(F)cc instructions llvm-svn: 6548
* Extensive changes to the way code generation occurs for functionVikram S. Adve2003-05-311-224/+359
| | | | | | | | | | | | | | call arguments and return values: Now all copy operations before and after a call are generated during selection instead of during register allocation. The values are copied to virtual registers (or to the stack), but in the former case these operands are marked with the correct physical registers according to the calling convention. Although this complicates scheduling and does not work well with live range analysis, it simplifies the machine-dependent part of register allocation. llvm-svn: 6465
* Reverting previous beautification changes.Vikram S. Adve2003-05-311-230/+233
| | | | llvm-svn: 6464
* Code beautification, no functional changes.Misha Brukman2003-05-311-233/+230
| | | | llvm-svn: 6459
* Moved and expanded convertOpcodeFromRegToImm() to conver more opcodes.Misha Brukman2003-05-301-448/+378
| | | | | | | Code beautification for the rest of the code: changed layout to match the rest of the code base. llvm-svn: 6446
* Added 'r' or 'i' annotations to instructions, as SparcInstr.def has changed.Misha Brukman2003-05-271-41/+79
| | | | | | | | | | Here I had to make one non-trivial change: add a function to get a version of the opcode that takes an immediate, given an opcode that takes all registers. This is required because sometimes it is not known at construction time which opcode is used because opcodes are passed around between functions. llvm-svn: 6375
* Added special register class containing (for now) %fsr.Vikram S. Adve2003-05-271-2/+2
| | | | | | | | Fixed spilling of %fcc[0-3] which are part of %fsr. Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. llvm-svn: 6339
* Bug fix: right shift for int divide-by-power-of-2 was incorrect forVikram S. Adve2003-05-251-11/+48
| | | | | | negative values. Need to add one to a negative value before right shift! llvm-svn: 6334
* Add support for compiling varargs functions.Vikram S. Adve2003-05-251-74/+144
| | | | llvm-svn: 6325
* Cleaned up code layout, spacing, etc. for readability purposes and to be moreMisha Brukman2003-05-211-192/+181
| | | | | | | | | consistent with the style of LLVM's code base (and itself! it's inconsistent in some places.) No functional changes were made. llvm-svn: 6265
* Namespacified `vector' and `cerr' to always use the `std::' namespace.Misha Brukman2003-05-211-18/+17
| | | | | | Eliminated `using' directives. llvm-svn: 6261
* Sparc instruction opcodes now all live under the `V9' namespace.Misha Brukman2003-05-201-231/+220
| | | | llvm-svn: 6249
* IntegerRegSize is always 8 for sparcChris Lattner2003-04-261-3/+2
| | | | llvm-svn: 5961
* Fix obvious type-oChris Lattner2003-04-251-2/+2
| | | | llvm-svn: 5932
* Move sparc specific code into the Sparc backendChris Lattner2003-01-151-2/+222
| | | | llvm-svn: 5317
* Use BuildMI moreChris Lattner2003-01-151-216/+141
| | | | llvm-svn: 5299
* Fix bug found by regtestsChris Lattner2003-01-151-9/+5
| | | | llvm-svn: 5294
* Use BuildMI more, Create*Instruction lessChris Lattner2003-01-151-37/+23
| | | | llvm-svn: 5291
* * Elimiante a bunch of functions from InstrSelectionSupport.h, replacing usersChris Lattner2003-01-151-26/+29
| | | | | | | of them with BUildMI calls instead. * Fix def information in instructions generated by prologepilog inserter llvm-svn: 5287
* * TargetData is no longer directly accessable from TMChris Lattner2002-12-281-40/+42
| | | | | | * s/unsigned int/unsigned/ llvm-svn: 5175
* Bug fix: align size for dynamic allocas according to stack pointerVikram S. Adve2002-10-291-19/+47
| | | | | | alignment restrictions. This is incomplete for one case. llvm-svn: 4397
* Fix minor bugChris Lattner2002-10-281-3/+3
| | | | llvm-svn: 4355
* Rename the redundant MachineOperand::getOperandType() to ↵Chris Lattner2002-10-281-1/+1
| | | | | | MachineOperand::getType() llvm-svn: 4331
* Changed `MachineCodeForMethod' to `MachineFunction'.Misha Brukman2002-10-281-3/+3
| | | | llvm-svn: 4301
* Removed misleading const keyword.Vikram S. Adve2002-10-141-1/+1
| | | | llvm-svn: 4169
* (1) Try to evaluate constant when multiplying 2 constants.Vikram S. Adve2002-10-131-29/+19
| | | | | | | | | (2) Use intelligent multiply selection code for array allocas. (3) Don't use cache padding for alloca'd stack slots! (4) Bug fix in handling call arguments: was not copying sixth FP arg to int reg. when calling a function with no prototype. llvm-svn: 4130
* Simplify Call translation slightly.Vikram S. Adve2002-09-281-25/+13
| | | | llvm-svn: 3963
* Overhaul integer conversions to match C++ ISO standard.Vikram S. Adve2002-09-271-95/+85
| | | | | | | Don't allow direct FP-to-uint conversion (must be eliminated by preselection). Address arithmetic for arrays is now entirely 64-bit so no sign-ext needed. llvm-svn: 3961
* Use ulong instead of uint for size expressions.Vikram S. Adve2002-09-161-2/+1
| | | | llvm-svn: 3744
* - Change getelementptr instruction to use long indexes instead of uintChris Lattner2002-09-111-13/+2
| | | | | | indexes for sequential types. llvm-svn: 3683
* Silly bug fix: Machine code vector could be empty for a no-op cast instruction,Vikram S. Adve2002-09-091-5/+9
| | | | | | e.g., cast double to double. llvm-svn: 3633
* -- Use size of pointer element type instead of pointer type in array offsets!Vikram S. Adve2002-09-051-27/+46
| | | | | | | -- A few bug fixes in casting between floats and ints. -- Use SRL reg, 0 instead of AND reg, 0xffffffff to clear high 32 bits. llvm-svn: 3579
* - Renamed Type::isIntegral() to Type::isInteger()Chris Lattner2002-09-031-19/+13
| | | | | | | - Added new method Type::isIntegral() that is the same as isInteger, but also accepts bool. llvm-svn: 3574
* Sign-extend values used to index arrays (and SimplifyVikram S. Adve2002-08-241-89/+28
| | | | | | | | SetOperandsForMemInstr significantly). Load and Store no longer have any indices. Eliminate spurious sign-extension on a cast to float/double. llvm-svn: 3498
* Eliminated the MemAccessInst class, folding contents into GEP class.Chris Lattner2002-08-221-4/+6
| | | | llvm-svn: 3488
* Eliminate bool, boolreg and boolconst nonterminals, and just useVikram S. Adve2002-08-221-17/+11
| | | | | | reg and Constant instead. llvm-svn: 3441
* Revise code generation for unary Not (boolean and bitwise), which isVikram S. Adve2002-08-151-24/+46
| | | | | | no longer a separate instruction but is instead implemented with XOR. llvm-svn: 3342
* Handle small unsigned results correctly by clearing high bits.Vikram S. Adve2002-08-131-34/+64
| | | | | | Bug fixes in casting to signed int values. llvm-svn: 3297
* * Removed extraneous #includesChris Lattner2002-08-091-12/+5
| | | | | | | * Fixed file headers to be consistent with the rest of LLVM * Other minor fixes llvm-svn: 3278
* Bug fix in SetOperandsForMemInstr: handle leading zeros correctlyVikram S. Adve2002-08-041-5/+9
| | | | | | when folding or not folding GEPs. llvm-svn: 3245
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