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* Fix a whole bunch of binary literals which were the wrong size. All were ↵Pete Cooper2014-08-071-1/+1
| | | | | | | | being silently zero extended to the correct width. The commit after this changes { } and 0bxx literals to be of type bits<n> and not int. This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us. llvm-svn: 215082
* [Sparc] Add support for decoding 'swap' instruction.Venkatraman Govindaraju2014-03-091-1/+1
| | | | llvm-svn: 203424
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-021-0/+12
| | | | | | backend. llvm-svn: 202670
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+8
| | | | llvm-svn: 202666
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-021-1/+2
| | | | llvm-svn: 202663
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-021-0/+13
| | | | llvm-svn: 202661
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-021-1/+7
| | | | llvm-svn: 202660
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-021-0/+4
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-021-1/+29
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ↵Venkatraman Govindaraju2014-03-021-16/+20
| | | | | | | | conditional registers as input. No functionality change. llvm-svn: 202614
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-021-1/+14
| | | | llvm-svn: 202610
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-021-5/+5
| | | | llvm-svn: 202604
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-011-18/+49
| | | | llvm-svn: 202602
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-011-6/+27
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-011-1/+2
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+35
| | | | llvm-svn: 202597
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-011-2/+2
| | | | llvm-svn: 202581
* [Sparc] Add support to decode negative simm13 operands in the sparc ↵Venkatraman Govindaraju2014-03-011-23/+27
| | | | | | disassembler. llvm-svn: 202578
* [Sparc] Add support for decoding call instructions in the sparc disassembler.Venkatraman Govindaraju2014-03-011-2/+3
| | | | llvm-svn: 202577
* [Sparc] Add support to disassemble sparc memory instructions.Venkatraman Govindaraju2014-03-011-16/+26
| | | | llvm-svn: 202575
* SPARC: Implement TRAP lowering. Matches what GCC emits.Benjamin Kramer2014-02-231-0/+3
| | | | llvm-svn: 201994
* [Sparc] Emit correct encoding for atomic instructions. Also, add support for ↵Venkatraman Govindaraju2014-02-071-8/+8
| | | | | | parsing CAS instructions to test the CAS encoding. llvm-svn: 200963
* [SparcV9] Use correct register class (I64RegClass) to hold the address of ↵Venkatraman Govindaraju2014-01-291-1/+1
| | | | | | _GLOBAL_OFFSET_TABLE_ in sparcv9. llvm-svn: 200368
* [Sparc] Add support for parsing floating point instructions.Venkatraman Govindaraju2014-01-121-123/+123
| | | | llvm-svn: 199033
* [Sparc] Add support for parsing jmpl instruction and make indirect call and ↵Venkatraman Govindaraju2014-01-101-13/+22
| | | | | | jmp instructions as aliases to jmpl. llvm-svn: 198909
* [Sparc] Multiclass for loads/stores. No functionality change intended.Venkatraman Govindaraju2014-01-091-116/+42
| | | | llvm-svn: 198893
* [Sparc] Add support for parsing branch instructions and conditional moves.Venkatraman Govindaraju2014-01-081-4/+7
| | | | llvm-svn: 198738
* [Sparc] Add support for parsing memory operands in sparc AsmParser.Venkatraman Govindaraju2014-01-071-2/+2
| | | | llvm-svn: 198658
* [Sparc] Add initial implementation of disassembler for sparcVenkatraman Govindaraju2014-01-061-38/+33
| | | | llvm-svn: 198591
* [Sparc] Add initial implementation of MC Code emitter for sparc.Venkatraman Govindaraju2014-01-051-2/+7
| | | | llvm-svn: 198533
* [Sparc] Add the initial implementation of an asm parser for sparc/sparcv9.Venkatraman Govindaraju2014-01-041-2/+17
| | | | llvm-svn: 198484
* [Sparc] Handle atomic loads/stores in sparc backend.Venkatraman Govindaraju2014-01-011-0/+40
| | | | llvm-svn: 198286
* [SparcV9]: Use SRL instead of SLL to clear top 32-bits in ctpop:i32. SLL ↵Venkatraman Govindaraju2014-01-011-2/+2
| | | | | | does not clear top 32 bit, only SRL does. llvm-svn: 198280
* [SparcV9] Use separate instruction patterns for 64 bit arithmetic ↵Venkatraman Govindaraju2013-12-291-18/+22
| | | | | | | | instructions instead of reusing 32 bit instruction patterns. This is done to avoid spilling the result of the 64-bit instructions to a 4-byte slot. llvm-svn: 198157
* [Sparc]: Implement LEA pattern for sparcv9.Venkatraman Govindaraju2013-11-241-4/+5
| | | | llvm-svn: 195575
* [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.Venkatraman Govindaraju2013-11-031-0/+6
| | | | llvm-svn: 193957
* [Sparc] Implement JIT for SPARC.Venkatraman Govindaraju2013-10-081-41/+41
| | | | | | | No new testcases. However, this patch makes all supported JIT testcases in test/ExecutionEngine pass on Sparc. llvm-svn: 192176
* [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use ↵Venkatraman Govindaraju2013-10-081-2/+2
| | | | | | DelaySlotFiller to fill the delay slot instead. llvm-svn: 192160
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-061-5/+7
| | | | llvm-svn: 192056
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-4/+4
| | | | | | addx/subx does not modify conditional codes whereas addxcc/subxx does. llvm-svn: 192053
* [Sparc] Use correct instruction pattern for CMPri.Venkatraman Govindaraju2013-09-221-1/+1
| | | | llvm-svn: 191180
* [Sparc] Make SPARC instructions' encoding well defined such that TableGen ↵Venkatraman Govindaraju2013-09-221-38/+41
| | | | | | can automatically generate code emitter. llvm-svn: 191168
* [Sparc] Clean up MOVcc instructions so that TableGen can encode them ↵Venkatraman Govindaraju2013-09-221-29/+49
| | | | | | correctly. No functionality change intended. llvm-svn: 191167
* [Sparc] Clean up branch instructions, so that TableGen can encode branch ↵Venkatraman Govindaraju2013-09-221-18/+22
| | | | | | conditions as well. No functionality change intended. llvm-svn: 191166
* [Sparc] Add support for TLS in sparc.Venkatraman Govindaraju2013-09-221-0/+49
| | | | llvm-svn: 191164
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-031-0/+9
| | | | llvm-svn: 189780
* [Sparc] Add long double (f128) instructions to sparc backend. Venkatraman Govindaraju2013-08-251-0/+108
| | | | llvm-svn: 189198
* Use register masks on SPARC call instructions.Jakob Stoklund Olesen2013-08-231-4/+1
| | | | llvm-svn: 189085
* [Sparc] Use HWEncoding instead of unused Num field in Sparc register ↵Venkatraman Govindaraju2013-08-201-2/+2
| | | | | | definitions. Also, correct the definitions of RETL and RET instructions. llvm-svn: 188738
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-081-13/+0
| | | | | | backend. llvm-svn: 183613
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