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* [Sparc] Add support for inline assembly constraint 'I'. Venkatraman Govindaraju2014-01-221-0/+7
| | | | llvm-svn: 199781
* [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that ↵Venkatraman Govindaraju2013-12-091-0/+3
| | | | | | umulo/smulo can be lowered on sparcv9 without an assertion error. llvm-svn: 196751
* [SparcV9] Handle i64 <-> float conversions in sparcv9 mode.Venkatraman Govindaraju2013-11-031-0/+6
| | | | llvm-svn: 193957
* [Sparc] Add support for TLS in sparc.Venkatraman Govindaraju2013-09-221-2/+7
| | | | llvm-svn: 191164
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-031-0/+17
| | | | llvm-svn: 189780
* The getRegForInlineAsmConstraint function should only accept MVT value types.Chad Rosier2013-06-221-1/+1
| | | | llvm-svn: 184642
* Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju2013-06-031-0/+1
| | | | llvm-svn: 183094
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-6/+6
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-141-0/+1
| | | | | | Test case by llvm-stress. llvm-svn: 179477
* Also put target flags on SPARC constant pool references.Jakob Stoklund Olesen2013-04-141-0/+1
| | | | | | | Constant pool entries are accessed exactly the same way as global variables. llvm-svn: 179471
* Add target flags to SPARC address operands.Jakob Stoklund Olesen2013-04-141-0/+3
| | | | | | | | | SDNodes and MachineOperands get target flags representing the %hi() and %lo() assembly annotations that eventually become relocations. Also define flags to be used by the 64-bit code models. llvm-svn: 179468
* Implement LowerCall_64 for the SPARC v9 64-bit ABI.Jakob Stoklund Olesen2013-04-071-0/+4
| | | | | | | There is still no support for byval arguments (which I don't think are needed) and varargs. llvm-svn: 178993
* Implement LowerReturn_64 for SPARC v9.Jakob Stoklund Olesen2013-04-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Integer return values are sign or zero extended by the callee, and structs up to 32 bytes in size can be returned in registers. The CC_Sparc64 CallingConv definition is shared between LowerFormalArguments_64 and LowerReturn_64. Function arguments and return values are passed in the same registers. The inreg flag is also used for return values. This is required to handle C functions returning structs containing floats and ints: struct ifp { int i; float f; }; struct ifp f(void); LLVM IR: define inreg { i32, float } @f() { ... ret { i32, float } %retval } The ABI requires that %retval.i is returned in the high bits of %i0 while %retval.f goes in %f1. Without the inreg return value attribute, %retval.i would go in %i0 and %retval.f would go in %f3 which is a more efficient way of returning %multiple values, but it is not ABI compliant for returning C structs. llvm-svn: 178966
* Add SPARC v9 support for select on 64-bit compares.Jakob Stoklund Olesen2013-04-041-0/+1
| | | | | | | | | | | This requires v9 cmov instructions using the %xcc flags instead of the %icc flags. Still missing: - Select floats on %xcc flags. - Select i64 on %fcc flags. llvm-svn: 178737
* Add 64-bit compare + branch for SPARC v9.Jakob Stoklund Olesen2013-04-031-1/+2
| | | | | | | | | | The same compare instruction is used for 32-bit and 64-bit compares. It sets two different sets of flags: icc and xcc. This patch adds a conditional branch instruction using the xcc flags for 64-bit compares. llvm-svn: 178621
* Add support for 64-bit calling convention.Jakob Stoklund Olesen2013-04-021-0/+12
| | | | | | | | | | | | This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. llvm-svn: 178523
* Add an I64Regs register class for 64-bit registers.Jakob Stoklund Olesen2013-04-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | We are going to use the same registers for 32-bit and 64-bit values, but in two different register classes. The I64Regs register class has a larger spill size and alignment. The addition of an i64 register class confuses TableGen's type inference, so it is necessary to clarify the type of some immediates and the G0 register. In 64-bit mode, pointers are i64 and should use the I64Regs register class. Implement getPointerRegClass() to dynamically provide the pointer register class depending on the subtarget. Use ptr_rc and iPTR for memory operands. Finally, add the i64 type to the IntRegs register class. This register class is not used to hold i64 values, I64Regs is for that. The type is required to appease TableGen's type checking in output patterns like this: def : Pat<(add i64:$a, i64:$b), (ADDrr $a, $b)>; SPARC v9 uses the same ADDrr instruction for i32 and i64 additions, and TableGen doesn't know to check the type of register sub-classes. llvm-svn: 178522
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-6/+1
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-1/+0
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-3/+2
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-2/+3
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-281-3/+2
| | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 llvm-svn: 151623
* Remove getRegClassForInlineAsmConstraint from sparc.Eric Christopher2011-06-291-3/+0
| | | | | | Part of rdar://9643582 llvm-svn: 134083
* Make the logic for determining function alignment more explicit. No ↵Eli Friedman2011-05-061-3/+0
| | | | | | functionality change. llvm-svn: 131012
* Generate correct Sparc32 ABI compliant code for functions that return a struct.Venkatraman Govindaraju2011-02-211-0/+2
| | | | llvm-svn: 126108
* Sparc backend: Venkatraman Govindaraju2011-01-211-1/+1
| | | | | | | Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. llvm-svn: 123997
* Implement RETURNADDR and FRAMEADDR lowering in SPARC backend.Venkatraman Govindaraju2011-01-121-1/+2
| | | | llvm-svn: 123310
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-071-0/+2
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-3/+3
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Use const qualifiers with TargetLowering. This eliminates severalDan Gohman2010-04-171-6/+6
| | | | | | | | | | | | | const_casts, and it reinforces the design of the Target classes being immutable. SelectionDAGISel::IsLegalToFold is now a static member function, because PIC16 uses it in an unconventional way. There is more room for API cleanup here. And PIC16's AsmPrinter no longer uses TargetLowering. llvm-svn: 101635
* Move per-function state out of TargetLowering subclasses and intoDan Gohman2010-04-171-3/+0
| | | | | | MachineFunctionInfo subclasses. llvm-svn: 101634
* Revert 95130.Evan Cheng2010-02-021-1/+1
| | | | llvm-svn: 95160
* Pass callsite return type to TargetLowering::LowerCall and use that to check ↵Evan Cheng2010-02-021-1/+1
| | | | | | sibcall eligibility. llvm-svn: 95130
* Eliminate target hook IsEligibleForTailCallOptimization.Evan Cheng2010-01-271-1/+1
| | | | | | | | | Target independent isel should always pass along the "tail call" property. Change target hook LowerCall's parameter "isTailCall" into a refernce. If the target decides it's impossible to honor the tail call request, it should set isTailCall to false to make target independent isel happy. llvm-svn: 94626
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-1/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* several major improvements to the sparc backend: support for weak linkageChris Lattner2009-09-151-1/+5
| | | | | | and PIC codegen. Patch by Venkatraman Govindaraju! llvm-svn: 81877
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-021-3/+3
| | | | llvm-svn: 80773
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-2/+2
| | | | | | own struct type. llvm-svn: 78610
* Major calling convention code refactoring.Dan Gohman2009-08-051-1/+23
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Don't override LowerArguments in the SPARC backend. In addition to Eli Friedman2009-07-191-3/+1
| | | | | | | | being more consistent with other backends, this makes the SPARC backend deal with functions with arguments with illegal types correctly, which fixes some tests in test/CodeGen/Generic. llvm-svn: 76375
* Update comments to make it clear that the function alignment is the Log2 of theBill Wendling2009-07-011-1/+1
| | | | | | bytes and not bytes. llvm-svn: 74624
* Add an "alignment" field to the MachineFunction object. It makes more sense toBill Wendling2009-06-301-0/+3
| | | | | | | | | | have the alignment be calculated up front, and have the back-ends obey whatever alignment is decided upon. This allows for future work that would allow for precise no-op placement and the like. llvm-svn: 74564
* Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowingDan Gohman2009-02-071-1/+1
| | | | | | ScheduleDAG's TLI member to use const. llvm-svn: 64018
* Make LowerCallTo and LowerArguments take a DebugLocDale Johannesen2009-01-301-1/+2
| | | | | | argument. Adjust all callers and overloaded versions. llvm-svn: 63444
* Teach DAGCombine to fold constant offsets into GlobalAddress nodes,Dan Gohman2008-10-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | and add a TargetLowering hook for it to use to determine when this is legal (i.e. not in PIC mode, etc.) This allows instruction selection to emit folded constant offsets in more cases, such as the included testcase, eliminating the need for explicit arithmetic instructions. This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp that attempted to achieve the same effect, but wasn't as effective. Also, fix handling of offsets in GlobalAddressSDNodes in several places, including changing GlobalAddressSDNode's offset from int to int64_t. The Mips, Alpha, Sparc, and CellSPU targets appear to be unaware of GlobalAddress offsets currently, so set the hook to false on those targets. llvm-svn: 57748
* Add rudimentary support for 'r' register operandAnton Korobeynikov2008-10-101-11/+18
| | | | llvm-svn: 57359
* Fix these enums' starting values to reflect the way thatDan Gohman2008-09-231-1/+1
| | | | | | instruction opcodes are now numbered. No functionality change. llvm-svn: 56497
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-3/+3
| | | | llvm-svn: 54128
* Replace some std::vectors that showed up in heap profiling withDan Gohman2008-06-301-2/+2
| | | | | | | | SmallVectors. Change the signature of TargetLowering::LowerArguments to avoid returning a vector by value, and update the two targets which still use this directly, Sparc and IA64, accordingly. llvm-svn: 52917
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