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* split sparc lowering out into SparcISelLowering.{cpp|h} to followChris Lattner2008-03-171-986/+1
| | | | | | best practices. llvm-svn: 48442
* refactor the LowerOperation code out to individual functions for Chris Lattner2008-03-171-173/+197
| | | | | | each lowering, which is 'best practice'. llvm-svn: 48441
* Default ISD::PREFETCH to expand.Evan Cheng2008-03-101-1/+0
| | | | llvm-svn: 48169
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-0/+1
| | | | | | and prefetchnta instructions. llvm-svn: 48042
* Sparc backend doesn't support debug info yet, mark the nodes as expand. ↵Chris Lattner2008-02-281-2/+6
| | | | | | | | This fixes a crash on test/DebugInfo/funccall.ll llvm-svn: 47709
* Fix CodeGen/Generic/storetrunc-fp.ll on sparc, PR2105Chris Lattner2008-02-281-1/+2
| | | | llvm-svn: 47707
* fix CodeGen/Generic/2008-01-25-dag-combine-mul.ll on sparc, PR2105Chris Lattner2008-02-281-0/+3
| | | | llvm-svn: 47706
* I cannot find a libgcc function for this builtin. Therefor expanding it to ↵Andrew Lenharth2008-02-161-1/+2
| | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213
* In TargetLowering::LowerCallTo, don't assert thatDuncan Sands2008-02-141-8/+14
| | | | | | | | | | | | | | | | | the return value is zero-extended if it isn't sign-extended. It may also be any-extended. Also, if a floating point value was returned in a larger floating point type, pass 1 as the second operand to FP_ROUND, which tells it that all the precision is in the original type. I think this is right but I could be wrong. Finally, when doing libcalls, set isZExt on a parameter if it is "unsigned". Currently isSExt is set when signed, and nothing is set otherwise. This should be right for all calls to standard library routines. llvm-svn: 47122
* Change how FP immediates are handled. Nate Begeman2008-02-141-3/+0
| | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121
* Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBitsDan Gohman2008-02-131-2/+2
| | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096
* Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.Dan Gohman2008-02-131-8/+8
| | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039
* Re-apply the memory operand changes, with a fix for the staticDan Gohman2008-02-061-7/+5
| | | | | | | | initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. llvm-svn: 46827
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* explicitly include Compiler.h instead of getting it from tblgen in the ↵Chris Lattner2008-02-031-0/+1
| | | | | | middle of a class. llvm-svn: 46676
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Revert 46556 and 46585. Dan please fix the PseudoSourceValue problem and ↵Evan Cheng2008-01-311-5/+7
| | | | | | re-commit. llvm-svn: 46623
* Create a new class, MemOperand, for describing memory referencesDan Gohman2008-01-311-7/+5
| | | | | | | | | | | | | | | | in the backend. Introduce a new SDNode type, MemOperandSDNode, for holding a MemOperand in the SelectionDAG IR, and add a MemOperand list to MachineInstr, and code to manage them. Remove the offset field from SrcValueSDNode; uses of SrcValueSDNode that were using it are all all using MemOperandSDNode now. Also, begin updating some getLoad and getStore calls to use the PseudoSourceValue objects. Most of this was written by Florian Brander, some reorganization and updating to TOT by me. llvm-svn: 46585
* Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a ↵Evan Cheng2008-01-301-4/+4
| | | | | | | | proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert instruction at the end. llvm-svn: 46562
* The last pieces needed for loading arbitraryDuncan Sands2008-01-231-1/+4
| | | | | | | | | | | | | | | precision integers. This won't actually work (and most of the code is dead) unless the new legalization machinery is turned on. While there, I rationalized the handling of i1, and removed some bogus (and unused) sextload patterns. For i1, this could result in microscopically better code for some architectures (not X86). It might also result in worse code if annotating with AssertZExt nodes turns out to be more harmful than helpful. llvm-svn: 46280
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-17/+17
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-1/+1
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-3/+4
| | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
* Set ISD::FPOW to Expand.Dan Gohman2007-10-111-0/+2
| | | | llvm-svn: 42881
* Fix CodeGen/Generic/BasicInstrs.llx on sparc by marking divremChris Lattner2007-10-101-1/+3
| | | | | | illegal. Thanks to gabor for pointing this out! llvm-svn: 42832
* Fold the adjust_trampoline intrinsic intoDuncan Sands2007-09-111-2/+0
| | | | | | | init_trampoline. There is now only one trampoline intrinsic. llvm-svn: 41841
* Support for trampolines, except for X86 codegen which isDuncan Sands2007-07-271-1/+3
| | | | | | still under discussion. llvm-svn: 40549
* Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551)Chris Lattner2007-07-131-0/+2
| | | | llvm-svn: 39813
* Assert when TLS is not implemented.Lauro Ramos Venancio2007-07-111-0/+3
| | | | llvm-svn: 39737
* Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits fromDan Gohman2007-06-221-2/+6
| | | | | | | | | TargetLowering to SelectionDAG so that they have more convenient access to the current DAG, in preparation for the ValueType routines being changed from standalone functions to members of SelectionDAG for the pre-legalize vector type changes. llvm-svn: 37704
* Refactoring of formal parameter flags. Enable properly use ofAnton Korobeynikov2007-03-071-2/+4
| | | | | | zext/sext/aext stuff. llvm-svn: 35008
* Simplify lowering and selection of exception ops.Jim Laskey2007-02-221-3/+0
| | | | llvm-svn: 34488
* Support to provide exception and selector registers.Jim Laskey2007-02-211-0/+3
| | | | llvm-svn: 34482
* Finish off bug 680, allowing targets to custom lower frame and returnNate Begeman2007-01-291-0/+4
| | | | | | address nodes. llvm-svn: 33636
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-1/+1
| | | | llvm-svn: 33537
* For PR950:Reid Spencer2006-12-311-19/+21
| | | | | | | | | | | | | | | | | | Three changes: 1. Convert signed integer types to signless versions. 2. Implement the @sext and @zext parameter attributes. Previously the type of an function parameter was used to determine whether it should be sign extended or zero extended before the call. This information is now communicated via the function type's parameter attributes. 3. The interface to LowerCallTo had to be changed in order to accommodate the parameter attribute information. Although it would have been convenient to pass in the FunctionType itself, there isn't always one present in the caller. Consequently, a signedness indication for the result type and for each parameter was provided for in the interface to this method. All implementations were changed to make the adjustment necessary. llvm-svn: 32788
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | llvm-svn: 32333
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-2/+3
| | | | | | of opcode and number of operands. llvm-svn: 31947
* Match tblegen changes.Evan Cheng2006-11-081-6/+7
| | | | llvm-svn: 31571
* All targets expand BR_JT for now.Evan Cheng2006-10-301-1/+2
| | | | llvm-svn: 31294
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-7/+6
| | | | llvm-svn: 30945
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-10/+10
| | | | llvm-svn: 30844
* Make use of getStore().Evan Cheng2006-10-051-8/+7
| | | | llvm-svn: 30759
* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-4/+4
| | | | | | extra operand to LOADX to specify the exact value extension type. llvm-svn: 30714
* Reflects MachineConstantPoolEntry changes.Evan Cheng2006-09-121-1/+1
| | | | llvm-svn: 30279
* SelectNodeTo now returns a SDNode*.Evan Cheng2006-08-261-2/+2
| | | | llvm-svn: 29901
* Select() no longer require Result operand by reference.Evan Cheng2006-08-261-6/+4
| | | | llvm-svn: 29898
* Match tblgen changes.Evan Cheng2006-08-261-6/+8
| | | | llvm-svn: 29895
* SelectNodeTo() may return a SDOperand that is different from the input.Evan Cheng2006-08-161-3/+3
| | | | llvm-svn: 29726
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