summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV
Commit message (Collapse)AuthorAgeFilesLines
...
* [RISCV] Support assembling TLS LA pseudo instructionsLewis Revill2019-05-232-0/+53
| | | | | | | | | This patch adds the pseudo instructions la.tls.ie and la.tls.gd, used in the initial-exec and global-dynamic TLS models respectively when addressing a global. The pseudo instructions are expanded in the assembly parser. llvm-svn: 361499
* [RISCV] Create a TargetInfo header. NFCRichard Trieu2019-05-158-7/+29
| | | | | | | | Move the declarations of getThe<Name>Target() functions into a new header in TargetInfo and make users of these functions include this new header. This fixes a layering problem. llvm-svn: 360732
* [RISCV] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-1110-33/+8
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure llvm-svn: 360505
* [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiersLewis Revill2019-04-238-4/+48
| | | | | | | | | This patch adds support for parsing and assembling the %tls_ie_pcrel_hi and %tls_gd_pcrel_hi modifiers. Differential Revision: https://reviews.llvm.org/D55342 llvm-svn: 358994
* [RISCV] Custom lower SHL_PARTS, SRA_PARTS, SRL_PARTSLuis Marques2019-04-162-3/+108
| | | | | | | | | When not optimizing for minimum size (-Oz) we custom lower wide shifts (SHL_PARTS, SRA_PARTS, SRL_PARTS) instead of expanding to a libcall. Differential Revision: https://reviews.llvm.org/D59477 llvm-svn: 358498
* [RISCV] Diagnose invalid second input register operand when using %tprel_addRoger Ferrer Ibanez2019-04-111-2/+26
| | | | | | | | | | | | | | | | | | | RISCVMCCodeEmitter::expandAddTPRel asserts that the second operand must be x4/tp. As we are not currently checking this in the RISCVAsmParser, the assert is easy to trigger due to wrong assembly input. This patch does a late check of this constraint. An alternative could be using a singleton register class for x4/tp similar to the current one for sp. Unfortunately it does not result in a good diagnostic. Because add is an overloaded mnemonic, if no matching is possible, the diagnostic of the first failing alternative seems to be used as the diagnostic itself. This means that this case the %tprel_add is diagnosed as an invalid operand (because the real add instruction only has 3 operands). Differential Revision: https://reviews.llvm.org/D60528 llvm-svn: 358183
* [RISCV] Put data smaller than eight bytes to small data sectionShiva Chen2019-04-112-0/+120
| | | | | | | | | | | Because of gp = sdata_start_address + 0x800, gp with signed twelve-bit offset could covert most of the small data section. Linker relaxation could transfer the multiple data accessing instructions to a gp base with signed twelve-bit offset instruction. Differential Revision: https://reviews.llvm.org/D57493 llvm-svn: 358150
* [AsmPrinter] refactor to remove remove AsmVariant. NFCNick Desaulniers2019-04-101-14/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The InlineAsm::AsmDialect is only required for X86; no architecture makes use of it and as such it gets passed around between arch-specific and general code while being unused for all architectures but X86. Since the AsmDialect is queried from a MachineInstr, which we also pass around, remove the additional AsmDialect parameter and query for it deep in the X86AsmPrinter only when needed/as late as possible. This refactor should help later planned refactors to AsmPrinter, as this difference in the X86AsmPrinter makes it harder to make AsmPrinter more generic. Reviewers: craig.topper Subscribers: jholewinski, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, sbc100, jgravelle-google, eraman, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, llvm-commits, peter.smith, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D60488 llvm-svn: 358101
* [RISCV] Support assembling TLS add and associated modifiersLewis Revill2019-04-049-11/+202
| | | | | | | | | | This patch adds support in the MC layer for parsing and assembling the 4-operand add instruction needed for TLS addressing. This also involves parsing the %tprel_hi, %tprel_lo and %tprel_add operand modifiers. Differential Revision: https://reviews.llvm.org/D55341 llvm-svn: 357698
* Test commit: Remove double variable assignmentLewis Revill2019-04-031-1/+1
| | | | llvm-svn: 357601
* [RISCV] Support assembling @plt symbol operandsAlex Bradbury2019-04-028-6/+34
| | | | | | | | | | This patch allows symbols appended with @plt to parse and assemble with the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55335 Patch by Lewis Revill. llvm-svn: 357470
* [RISCV] Attach VK_RISCV_CALL to symbols upon creationAlex Bradbury2019-04-016-9/+57
| | | | | | | | | | | | | | | | | This patch replaces the addition of VK_RISCV_CALL in RISCVMCCodeEmitter by creating the RISCVMCExpr when tail/call are parsed, or in the codegen case when the callee symbols are created. This required adding a new CallSymbol operand to allow only adding VK_RISCV_CALL to tail/call instructions. This patch will allow further expansion of parsing and codegen to easily include PLT symbols which must generate the R_RISCV_CALL_PLT relocation. Differential Revision: https://reviews.llvm.org/D55560 Patch by Lewis Revill. llvm-svn: 357396
* [RISCV] Generate address sequences suitable for mcmodel=mediumAlex Bradbury2019-04-016-35/+110
| | | | | | | | | | | | | | | | | This patch adds an implementation of a PC-relative addressing sequence to be used when -mcmodel=medium is specified. With absolute addressing, a 'medium' codemodel may cause addresses to be out of range. This is because while 'medium' implies a 2 GiB addressing range, this 2 GiB can be at any offset as opposed to 'small', which implies the first 2 GiB only. Note that LLVM/Clang currently specifies code models differently to GCC, where small and medium imply the same functionality as GCC's medlow and medany respectively. Differential Revision: https://reviews.llvm.org/D54143 Patch by Lewis Revill. llvm-svn: 357393
* [RISCV] Add seto pattern expansionLuis Marques2019-04-013-3/+11
| | | | | | | | | Adds a `seto` pattern expansion. Without it the lowerings of `fcmp one` and `fcmp ord` would be inefficient due to an unoptimized double negation. Differential Revision: https://reviews.llvm.org/D59699 llvm-svn: 357378
* [RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to ↵Alex Bradbury2019-04-012-2/+21
| | | | | | | | | | | | | | | | | | linker relaxation) A pcrel_lo will point to the associated pcrel_hi fixup which in turn points to the real target. RISCVMCExpr::evaluatePCRelLo will work around this indirection in order to allow the fixup to be evaluate properly. However, if relocations are forced (e.g. due to linker relaxation is enabled) then its evaluation is undesired and will result in a relocation with the wrong target. This patch modifies evaluatePCRelLo so it will not try to evaluate if the fixup will be forced as a relocation. A new helper method is added to RISCVAsmBackend to query this. Differential Revision: https://reviews.llvm.org/D59686 llvm-svn: 357374
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard ↵Alex Bradbury2019-03-303-17/+128
| | | | | | | | | | | | | | | | | | | | float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
* [RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))Alex Bradbury2019-03-301-0/+11
| | | | | | | | | | | | The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32 (necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP, this will result in a FP load from the constant pool followed by a store to the stack and two integer loads from the stack (necessary as there is no way to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper to just materialise integers for the lo and hi parts of the FP constant, so do that instead. llvm-svn: 357341
* [RISCV] Improve codegen for icmp {ne,eq} with a constantLuis Marques2019-03-261-0/+4
| | | | | | | | | Adds two patterns to improve the codegen of GPR value comparisons with small constants. Instead of first loading the constant into another register and then doing an XOR of those registers, these patterns directly use the constant as an XORI immediate. llvm-svn: 356990
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-229-15/+67
| | | | | | | | | | | | | | | | | | | | | The RISC-V ISA defines RV32E as an alternative "base" instruction set encoding, that differs from RV32I by having only 16 rather than 32 registers. This patch adds basic definitions for RV32E as well as MC layer support (assembling, disassembling) and tests. The only supported ABI on RV32E is ILP32E. Add a new RISCVFeatures::validate() helper to RISCVUtils which can be called from codegen or MC layer libraries to validate the combination of TargetTriple and FeatureBitSet. Other targets have similar checks (e.g. erroring if SPE is enabled on PPC64 or oddspreg + o32 ABI on Mips), but they either duplicate the checks (Mips), or fail to check for both codegen and MC codepaths (PPC). Codegen for the ILP32E ABI support and RV32E codegen are left for a future patch/patches. Differential Revision: https://reviews.llvm.org/D59470 llvm-svn: 356744
* [RISCV] Optimize emission of SELECT sequencesAlex Bradbury2019-03-221-17/+90
| | | | | | | | | | | | | | | | | | | This patch optimizes the emission of a sequence of SELECTs with the same condition, avoiding the insertion of unnecessary control flow. Such a sequence often occurs when a SELECT of values wider than XLEN is legalized into two SELECTs with legal types. We have identified several use cases where the SELECTs could be interleaved with other instructions. Therefore, we extend the sequence to include non-SELECT instructions if we are able to detect that the non-SELECT instructions do not impact the optimization. This patch supersedes https://reviews.llvm.org/D59096, which attempted to address this issue by introducing a new SelectionDAG node. Hat tip to Eli Friedman for his feedback on how to best handle this issue. Differential Revision: https://reviews.llvm.org/D59355 Patch by Luís Marques. llvm-svn: 356741
* [RISCV] Allow conversion of CC logic to bitwise logicAlex Bradbury2019-03-221-0/+4
| | | | | | | | | | | | | Indicates in the TargetLowering interface that conversions from CC logic to bitwise logic are allowed. Adds tests that show the benefit when optimization opportunities are detected. Also adds tests that show that when the optimization is not applied correct code is generated (but opportunities for other optimizations remain). Differential Revision: https://reviews.llvm.org/D59596 Patch by Luís Marques. llvm-svn: 356740
* [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cppAlex Bradbury2019-03-171-11/+17
| | | | | | Contains common logic to match a string to a register name. llvm-svn: 356330
* [RISCV] Fix RISCVAsmParser::ParseRegister and add testsAlex Bradbury2019-03-171-5/+7
| | | | | | | | | | | RISCVAsmParser::ParseRegister is called from AsmParser::parseRegisterOrNumber, which in turn is called when processing CFI directives. The RISC-V implementation wasn't setting RegNo, and so was incorrect. This patch address that and adds cfi directive tests that demonstrate the fix. A follow-up patch will factor out the register parsing logic shared between ParseRegister and parseRegister. llvm-svn: 356329
* [RISCV] Fix rL356123Alex Bradbury2019-03-141-2/+2
| | | | | | The wrong version of the patch was committed. This fixes typos that broke the build. llvm-svn: 356124
* [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor ↵Alex Bradbury2019-03-142-7/+10
| | | | | | | | | | | | | RISCVRegisterInfo refactoring The CSR renaming further prepares the way for an upcoming patch adding support for more RISC-V ABIs. Modify RISCVRegisterInfo::getCalleeSavedRegs and RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>() once rather than multiple times. llvm-svn: 356123
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-1/+3
| | | | | | | | This follows similar logic in the ARM and Mips backends, and allows the free use of s0 in functions without a dedicated frame pointer. The changes in callee-saved-gprs.ll most clearly show the effect of this patch. llvm-svn: 356063
* [RISCV] Replace incorrect use of sizeof with array_lengthofAlex Bradbury2019-03-131-3/+3
| | | | | | | RISCVDisassembler was incorrectly using sizeof(Arr) when it should have used sizeof(Arr)/sizeof(Arr[0]). Update to use array_lengthof instead. llvm-svn: 356035
* [RISCV][MC] Find matching pcrel_hi fixup in more cases.Eli Friedman2019-03-121-4/+12
| | | | | | | | | | | | | | | | | If a symbol points to the end of a fragment, instead of searching for fixups in that fragment, search in the next fragment. Fixes spurious assembler error with subtarget change next to "la" pseudo-instruction, or expanded equivalent. Alternate proposal to fix the problem discussed in https://reviews.llvm.org/D58759. Testcase by Ana Pazos. Differential Revision: https://reviews.llvm.org/D58943 llvm-svn: 355946
* [RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64AAlex Bradbury2019-03-111-0/+4
| | | | | | | | | | | | | | | | AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison. This requires an extension of the value which, by default, is a zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension. This mismatch of extensions causes the comparison to fail when the compared value is negative. This change overrides TargetLowering::getExtendForAtomicOps for RISC-V so it does a sign-extension instead. Differential Revision: https://reviews.llvm.org/D58829 Patch by Ferran Pallarès Roca. llvm-svn: 355869
* [RISCV] Allow fp as an alias of s0Alex Bradbury2019-03-111-1/+1
| | | | | | | | | | | The RISC-V Assembly Programmer's Manual defines fp as another alias of x8. However, our tablegen rules only recognise s0. This patch adds fp as another alias of x8. GCC also accepts fp. Differential Revision: https://reviews.llvm.org/D59209 Patch by Ferran Pallarès Roca. llvm-svn: 355867
* [RISCV][NFC] Convert some MachineBaiscBlock::iterator(MI) to MI.getIterator()Alex Bradbury2019-03-112-4/+4
| | | | llvm-svn: 355864
* [RISCV][NFC] Minor refactoring of CC_RISCVAlex Bradbury2019-03-091-7/+7
| | | | | | | Immediately check if we need to early-exit as we have a return value that can't be returned directly. Also tweak following if/else. llvm-svn: 355773
* [RISCV][NFC] Split out emitSelectPseudo from EmitInstrWithCustomInserterAlex Bradbury2019-03-091-16/+19
| | | | | | It's cleaner and more consistent to have a separate helper function here. llvm-svn: 355772
* [RISCV] Support -target-abi at the MC layer and for codegenAlex Bradbury2019-03-0910-15/+131
| | | | | | | | | | | | | | | | This patch adds proper handling of -target-abi, as accepted by llvm-mc and llc. Lowering (codegen) for the hard-float ABIs will follow in a subsequent patch. However, this patch does add MC layer support for the hard float and RVE ABIs (emission of the appropriate ELF flags https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#-file-header). ABI parsing must be shared between codegen and the MC layer, so we add computeTargetABI to RISCVUtils. A warning will be printed if an invalid or unrecognized ABI is given. Differential Revision: https://reviews.llvm.org/D59023 llvm-svn: 355771
* [RISCV] Allow access to FP CSRs without F extensionAna Pazos2019-03-081-2/+0
| | | | | | | | | | | | | | | | | | Summary: Floating-point CSRs should be accessible even when F extension is not enabled. But pseudo instructions that access floating point CSRs still require the F extension. GNU tools already implement this behavior. RISC-V spec is pending update to reflect this behavior and to extend it to pseudo instructions that access floating point CSRs. Reviewers: asb Reviewed By: asb Subscribers: asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, llvm-commits Differential Revision: https://reviews.llvm.org/D58932 llvm-svn: 355753
* [RISCV][NFC] IsEligibleForTailCallOptimization -> ↵Alex Bradbury2019-02-212-9/+8
| | | | | | | | isEligibleForTailCallOptimization Also clang-format the modified hunks. llvm-svn: 354584
* [RISCV] Add implied zero offset load/store alias patternsAlex Bradbury2019-02-214-0/+81
| | | | | | | | | | Allow load/store instructions with implied zero offset for compatibility with GNU assembler. Differential Revision: https://reviews.llvm.org/D57141 Patch by James Clarke. llvm-svn: 354581
* [RISCV] Implement pseudo instructions for load/store from a symbol address.Kito Cheng2019-02-205-14/+137
| | | | | | | | | | | | | Summary: Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address. Reviewers: asb, apazos, rogfer01, jrtc27 Differential Revision: https://reviews.llvm.org/D50496 llvm-svn: 354430
* [RISCV][NFC] Move some std::string to StringRefAlex Bradbury2019-02-193-5/+5
| | | | llvm-svn: 354333
* [RISCV] Add assembler support for LA pseudo-instructionAlex Bradbury2019-02-152-18/+76
| | | | | | | | | | This patch also introduces the emitAuipcInstPair helper, which is then used for both emitLoadAddress and emitLoadLocalAddress. Differential Revision: https://reviews.llvm.org/D55325 Patch by James Clarke. llvm-svn: 354111
* [RISCV] Support assembling %got_pcrel_hi operatorAlex Bradbury2019-02-158-8/+32
| | | | | | | Differential Revision: https://reviews.llvm.org/D55279 Patch by James Clarke. llvm-svn: 354110
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This patch accompanies the RFC posted here: http://lists.llvm.org/pipermail/llvm-dev/2018-October/127239.html This patch adds a new CallBr IR instruction to support asm-goto inline assembly like gcc as used by the linux kernel. This instruction is both a call instruction and a terminator instruction with multiple successors. Only inline assembly usage is supported today. This also adds a new INLINEASM_BR opcode to SelectionDAG and MachineIR to represent an INLINEASM block that is also considered a terminator instruction. There will likely be more bug fixes and optimizations to follow this, but we felt it had reached a point where we would like to switch to an incremental development model. Patch by Craig Topper, Alexander Ivchenko, Mikhail Dvoretckii Differential Revision: https://reviews.llvm.org/D53765 llvm-svn: 353563
* [RISCV] Implement RV64D codegenAlex Bradbury2019-02-012-4/+30
| | | | | | | | | | | | This patch: * Adds necessary RV64D codegen patterns * Modifies CC_RISCV so it will properly handle f64 types (with soft float ABI) Note that in general there is no reason to try to select fcvt.w[u].d rather than fcvt.l[u].d for i32 conversions because fptosi/fptoui produce poison if the input won't fit into the target type. Differential Revision: https://reviews.llvm.org/D53237 llvm-svn: 352833
* [RISCV] Add RV64F codegen supportAlex Bradbury2019-01-313-2/+130
| | | | | | | | | | | | | This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 llvm-svn: 352807
* [RISCV] Insert R_RISCV_ALIGN relocation type and Nops for code alignment ↵Shiva Chen2019-01-304-1/+70
| | | | | | | | | | | | | | | | | | | | when linker relaxation enabled Linker relaxation may change code size. We need to fix up the alignment of alignment directive in text section by inserting Nops and R_RISCV_ALIGN relocation type. So then linker could satisfy the alignment by removing Nops. To do this: 1. Add shouldInsertExtraNopBytesForCodeAlign target hook to calculate the Nops we need to insert. 2. Add shouldInsertFixupForCodeAlign target hook to insert R_RISCV_ALIGN fixup type. Differential Revision: https://reviews.llvm.org/D47755 llvm-svn: 352616
* [RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FDAlex Bradbury2019-01-251-3/+28
| | | | | | | | | | | | | DAGCombiner::visitBITCAST will perform: fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) As shown in double-bitmanip-dagcombines.ll, this can be advantageous. But RV32FD doesn't use bitcast directly (as i64 isn't a legal type), and instead uses RISCVISD::SplitF64. This patch adds an equivalent DAG combine for SplitF64. llvm-svn: 352247
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-253-3/+18
| | | | | | This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
* [RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64MAlex Bradbury2019-01-253-49/+55
| | | | | | | | | | | | | | Follow the same custom legalisation strategy as used in D57085 for variable-length shifts (see that patch summary for more discussion). Although we may lose out on some late-stage DAG combines, I think this custom legalisation strategy is ultimately easier to reason about. There are some codegen changes in rv64m-exhaustive-w-insts.ll but they are all neutral in terms of the number of instructions. Differential Revision: https://reviews.llvm.org/D57096 llvm-svn: 352171
* [RISCV] Custom-legalise 32-bit variable shifts on RV64Alex Bradbury2019-01-253-67/+105
| | | | | | | | | | | | | | | | | | | | | | | | | The previous DAG combiner-based approach had an issue with infinite loops between the target-dependent and target-independent combiner logic (see PR40333). Although this was worked around in rL351806, the combiner-based approach is still potentially brittle and can fail to select the 32-bit shift variant when profitable to do so, as demonstrated in the pr40333.ll test case. This patch instead introduces target-specific SelectionDAG nodes for SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a good example of how this approach can improve codegen. This adds DAG combine that does SimplifyDemandedBits on the operands (only lower 32-bits of first operand and lower 5 bits of second operand are read). This seems better than implementing SimplifyDemandedBitsForTargetNode as there is no guarantee that would be called (and it's not for e.g. the anyext return test cases). Also implements ComputeNumSignBitsForTargetNode. There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new instruction sequences are semantically equivalent. Differential Revision: https://reviews.llvm.org/D57085 llvm-svn: 352169
* Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"Ana Pazos2019-01-243-18/+3
| | | | | | | | This reverts commit ccfb060ecb5d7e18ea729455660484d576bde2cc. Some tests need to to fixed before reapplying this commit. llvm-svn: 352014
OpenPOWER on IntegriCloud