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path: root/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
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* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+48
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
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