| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ↵ | Alex Bradbury | 2018-04-12 | 1 | -3/+14 |
| | | | | | | | | | | | | | | | | | conv fadd.d is required in order to force floating point registers to be used in test code, as parameters are passed in integer registers in the soft float ABI. Much of this patch is concerned with support for passing f64 on RV32D with a soft-float ABI. Similar to Mips, introduce pseudoinstructions to build an f64 out of a pair of i32 and to split an f64 to a pair of i32. BUILD_PAIR and EXTRACT_ELEMENT can't be used, as a BITCAST to i64 would be necessary, but i64 is not a legal type. llvm-svn: 329871 | ||||
| * | [RISCV] Support for varargs | Alex Bradbury | 2018-01-10 | 1 | -0/+44 |
| Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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