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path: root/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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* [RISCV] Fix std::advance slownessAna Pazos2018-08-241-2/+1
| | | | | | | | | | | | | | | | | | Summary: It seems std::advance template is treating "-MFI.getCalleeSavedInfo().size()" as a large unsigned value", causing slowness. Thanks to Henrik Gustafsson for reporting the issue. Reviewers: asb Reviewed By: asb Subscribers: llvm-commits, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, asb Differential Revision: https://reviews.llvm.org/D51148 llvm-svn: 340669
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+30
| | | | | | | | | | | | | | | | | | | | | - Save/restore only registers that are used. This includes Callee saved registers and Caller saved registers (arguments and temporaries) for integer and FP registers. - If there is a call in the interrupt handler, save/restore all Caller saved registers (arguments and temporaries) and all FP registers. - Emit special return instructions depending on "interrupt" attribute type. Based on initial patch by Zhaoshi Zheng. Reviewers: asb Reviewed By: asb Subscribers: rkruppe, the_o, MartinMosbeck, brucehoult, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, llvm-commits Differential Revision: https://reviews.llvm.org/D48411 llvm-svn: 338047
* [RISCV] Preserve stack space for outgoing arguments when the function ↵Shiva Chen2018-03-201-15/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | contain variable size objects E.g. bar (int x) { char p[x]; push outgoing variables for foo. call foo } We need to generate stack adjustment instructions for outgoing arguments by eliminateCallFramePseudoInstr when the function contains variable size objects to avoid outgoing variables corrupt the variable size object. Default hasReservedCallFrame will return !hasFP(). We don't want to generate extra sp adjustment instructions when hasFP() return true, So We override hasReservedCallFrame as !hasVarSizedObjects(). Differential Revision: https://reviews.llvm.org/D43752 llvm-svn: 327938
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-19/+22
| | | | llvm-svn: 322839
* [RISCV] Reserve an emergency spill slot for the register scavenger when ↵Alex Bradbury2018-01-111-0/+19
| | | | | | | | | | | necessary Although the register scavenger can often find a spare register, an emergency spill slot is needed to guarantee success. Reserve this slot in cases where the function is known to have a large stack (meaning the scavenger may be needed when forming stack addresses). llvm-svn: 322269
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-7/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D40807 llvm-svn: 322216
* [RISCV] Support for varargsAlex Bradbury2018-01-101-3/+12
| | | | | | | | | | | | Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215
* [RISCV] Implement prolog and epilog insertionAlex Bradbury2017-12-111-2/+145
| | | | | | | | | | As frame pointer elimination isn't implemented until a later patch and we make extensive use of update_llc_test_checks.py, this changes touches a lot of the RISC-V tests. Differential Revision: https://reviews.llvm.org/D39849 llvm-svn: 320357
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-0/+29
| | | | | | | | | | | | | | | | Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+29
This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188
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