| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Codegen support for memory operations on global addresses | Alex Bradbury | 2017-11-08 | 1 | -1/+6 |
| | | | | | | | Differential Revision: https://reviews.llvm.org/D39103 llvm-svn: 317688 | ||||
| * | [RISCV] Initial codegen support for ALU operations | Alex Bradbury | 2017-10-19 | 1 | -0/+67 |
| This adds the minimum necessary to support codegen for simple ALU operations on RV32. Prolog and epilog insertion, support for memory operations etc etc follow in future patches. Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is reviewed and lands. Differential Revision: https://reviews.llvm.org/D29933 llvm-svn: 316188 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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