| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [RISCV] Prepare for the use of variable-sized register classes | Alex Bradbury | 2017-10-19 | 1 | -8/+8 |
| | | | | | | | | | | | While parameterising by XLen, also take the opportunity to clean up the formatting of the RISCV .td files. This commit unifies the in-tree code with my patchset at <https://github.com/lowrisc/riscv-llvm>. llvm-svn: 316159 | ||||
| * | [RISCV] Add support for disassembly | Alex Bradbury | 2017-09-17 | 1 | -0/+135 |
| This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s has been updated appropriately. Differential Revision: https://reviews.llvm.org/D23567 llvm-svn: 313486 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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