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path: root/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Allow parsing dot '.' in assemblySam Elliott2019-07-121-0/+1
* [RISCV] Add break; to the last switch caseFangrui Song2019-07-011-0/+1
* [RISCV] Add pseudo instruction for calls with explicit registerLewis Revill2019-06-261-0/+4
* [RISCV] Allow parsing immediates that use tilde & exclaimLewis Revill2019-06-191-0/+4
* [RISCV] Fix failure to parse parenthesized immediatesLewis Revill2019-06-191-3/+8
* Revert CMake: Make most target symbols hidden by defaultTom Stellard2019-06-111-1/+1
* CMake: Make most target symbols hidden by defaultTom Stellard2019-06-101-1/+1
* [RISCV] Support assembling TLS LA pseudo instructionsLewis Revill2019-05-231-0/+43
* [RISCV] Create a TargetInfo header. NFCRichard Trieu2019-05-151-0/+1
* [RISCV] Support assembling %tls_{ie,gd}_pcrel_hi modifiersLewis Revill2019-04-231-4/+9
* [RISCV] Diagnose invalid second input register operand when using %tprel_addRoger Ferrer Ibanez2019-04-111-2/+26
* [RISCV] Support assembling TLS add and associated modifiersLewis Revill2019-04-041-7/+25
* [RISCV] Support assembling @plt symbol operandsAlex Bradbury2019-04-021-2/+12
* [RISCV] Attach VK_RISCV_CALL to symbols upon creationAlex Bradbury2019-04-011-0/+34
* [RISCV] Add basic RV32E definitions and MC layer supportAlex Bradbury2019-03-221-4/+9
* [RISCV][NFC] Factor out matchRegisterNameHelper in RISCVAsmParser.cppAlex Bradbury2019-03-171-11/+17
* [RISCV] Fix RISCVAsmParser::ParseRegister and add testsAlex Bradbury2019-03-171-5/+7
* [RISCV] Implement pseudo instructions for load/store from a symbol address.Kito Cheng2019-02-201-1/+80
* [RISCV] Add assembler support for LA pseudo-instructionAlex Bradbury2019-02-151-17/+71
* [RISCV] Support assembling %got_pcrel_hi operatorAlex Bradbury2019-02-151-4/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV][MC] Add support for evaluating constant symbols as immediatesAlex Bradbury2019-01-101-8/+1
* [RISCV][MC] Accept %lo and %pcrel_lo on operands to liAlex Bradbury2019-01-031-3/+15
* [RISCV] Support .option push and .option popAlex Bradbury2018-11-281-1/+46
* [RISCV] Introduce the RISCVMatInt::generateInstSeq helperAlex Bradbury2018-11-151-72/+16
* [RISCV] Support .option relax and .option norelaxAlex Bradbury2018-11-121-1/+42
* [RISCV] Support named operands for CSR instructions.Ana Pazos2018-10-041-54/+157
* [RISCV][MC] Modify evaluateConstantImm interface to allow reuse from addExprAlex Bradbury2018-09-201-35/+34
* [RISCV][MC] Improve parsing of jal/j operandsAlex Bradbury2018-09-201-2/+20
* [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand typeAlex Bradbury2018-09-181-30/+35
* [RISCV][MC] Reject bare symbols for the simm12 operand typeAlex Bradbury2018-09-181-3/+5
* [RISCV][MC] Tighten up checking of sybol operands to lui and auipcAlex Bradbury2018-09-181-9/+32
* [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand typesAna Pazos2018-09-131-14/+4
* [RISCV] Fixed SmallVector.h Assertion `idx < size()'Ana Pazos2018-08-301-1/+17
* [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.Ana Pazos2018-08-241-0/+18
* [RISCV] Fix incorrect use of MCInstBuilderRoger Ferrer Ibanez2018-08-141-8/+6
* [RISCV] Add "lla" pseudo-instruction to assemblerRoger Ferrer Ibanez2018-08-091-3/+64
* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-071-10/+147
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-171-1/+2
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-171-0/+4
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-111-1/+77
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ...Alex Bradbury2018-04-251-9/+12
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+14
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-59/+10
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-10/+59
* [NFC] fix trivial typos in comments and error messageHiroshi Inoue2018-04-091-1/+1
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-061-2/+10
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-221-5/+8
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-2/+3
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-021-4/+21
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