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path: root/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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* [RISCV] Change shift amount operand of RVC shift instructions to ↵Alex Bradbury2017-12-151-2/+16
| | | | | | | | | | | | | | uimmlog2xlennonzero c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-131-16/+16
| | | | | | | We sort these helper functions and td definitions by bit width. simm6 was previously out-of-order with respect to the others. llvm-svn: 320559
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-2/+67
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+12
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-071-0/+48
| | | | | | | | | | extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-11/+35
| | | | llvm-svn: 320024
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+64
| | | | | | | | | | | As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+36
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-6/+31
| | | | llvm-svn: 317791
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
| | | | | | | This is necessary to avoid an assertion in the included test case and similar assembler inputs. llvm-svn: 316168
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
| | | | llvm-svn: 316167
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+2
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-20/+162
| | | | | | | | | | | | | %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-171-11/+145
| | | | | | | | | | This patch supports all RV32I instructions as described in the RISC-V manual. A future patch will add support for pseudoinstructions and other instruction expansions (e.g. 0-arg fence -> fence iorw, iorw). Differential Revision: https://reviews.llvm.org/D23566 llvm-svn: 313485
* [RISCV][NFC] Fix sorting of includes in lib/Target/RISCVAlex Bradbury2017-09-061-5/+5
| | | | llvm-svn: 312624
* [RISCV] Fix warning about unused getSubtargetFeatureName()Alex Bradbury2017-08-081-1/+0
| | | | llvm-svn: 310375
* [RISCV] Add basic RISCVAsmParser (missing files)Alex Bradbury2017-08-081-0/+373
This commit adds the files missing from rL310361. Apologies for the noise. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310363
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