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* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-071-10/+147
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. The actual expansion to real instructions is similar to the expansion performed by the GNU Assembler. This patch supersedes D41949. Differential Revision: https://reviews.llvm.org/D46118 Patch by Mario Werner. llvm-svn: 334203
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-171-1/+2
| | | | | | | | | | | | | | | | Summary: This patch implements MC support for tail psuedo instruction. A follow-up patch implements the codegen support as well as handling of the indirect tail pseudo instruction. Reviewers: asb, apazos Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, llvm-commits Differential Revision: https://reviews.llvm.org/D46221 llvm-svn: 332634
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-171-0/+4
| | | | | | | | | | These directives are recognised by gas. Support is added through the use of addAliasForDirective. Also match RISC-V gcc in preferring .half and .word for 16-bit and 32-bit data directives. llvm-svn: 332574
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-111-1/+77
| | | | | | | | | | These directives allow the 'C' (compressed) extension to be enabled/disabled within a single file. Differential Revision: https://reviews.llvm.org/D45864 Patch by Kito Cheng llvm-svn: 332107
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ↵Alex Bradbury2018-04-251-9/+12
| | | | | | | | | | coincides with a register name Previously `call zero`, `call f0` etc would fail. This leads to compilation failures if building programs that define functions with those names and using -save-temps. llvm-svn: 330846
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To do this: 1. Add PseudoCALLIndirct to match indirect function call. 2. Add PseudoCALL to support parsing and print pseudo `call` in assembly 3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type while encoding: auipc ra, func jalr ra, ra, 0 If we expand PseudoCALL before emitting assembly, we will see auipc and jalr pair when compile with -S. It's hard for assembly parser to parsing this pair and identify it's semantic is function call and then insert R_RISCV_CALL relocation type. Although we could insert R_RISCV_PCREL_HI20 and R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL. Due to RISCV relocation design, auipc and jalr pair only can relax to jal with R_RISCV_CALL + R_RISCV_RELAX relocation types. We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before emitting assembly(RISCVAsmPrinter) because we want to preserve call pseudoinstruction in assembly code. It's more readable and assembly parser could identify call assembly and insert R_RISCV_CALL relocation type. Differential Revision: https://reviews.llvm.org/D45859 llvm-svn: 330826
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-59/+10
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-10/+59
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [NFC] fix trivial typos in comments and error messageHiroshi Inoue2018-04-091-1/+1
| | | | | | "is is" -> "is", "are are" -> "are" llvm-svn: 329546
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-061-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-221-5/+8
| | | | | | | | | | | | Implement c.lui immediate constraint to [1, 31] and [0xfffe0, 0xfffff]. The RISC-V ISA describes the constraint as [1, 63], with that value being loaded in to bits 17-12 of the destination register and sign extended from bit 17. Therefore, this 6-bit immediate can represent values in the ranges [1, 31] and [0xfffe0, 0xfffff]. Differential Revision: https://reviews.llvm.org/D42834 llvm-svn: 325792
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-2/+3
| | | | llvm-svn: 324303
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-021-4/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D42782 llvm-svn: 324055
* [RISCV] Change shift amount operand of RVC shift instructions to ↵Alex Bradbury2017-12-151-2/+16
| | | | | | | | | | | | | | uimmlog2xlennonzero c.slli/c.srli/c.srai allow a 5-bit shift in RV32C and a 6-bit shift in RV64C. This patch adds uimmlog2xlennonzero to reflect this constraint as well as tests. Differential Revision: https://reviews.llvm.org/D41216 Patch by Shiva Chen. llvm-svn: 320799
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-131-16/+16
| | | | | | | We sort these helper functions and td definitions by bit width. simm6 was previously out-of-order with respect to the others. llvm-svn: 320559
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-2/+67
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+12
| | | | | | | | Differential Revision: https://reviews.llvm.org/D40002 Patch by Shiva Chen. llvm-svn: 320038
* [RISCV] MC layer support for load/store instructions of the C (compressed) ↵Alex Bradbury2017-12-071-0/+48
| | | | | | | | | | extension Differential Revision: https://reviews.llvm.org/D40001 Patch by Shiva Chen. llvm-svn: 320037
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-11/+35
| | | | llvm-svn: 320024
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+64
| | | | | | | | | | | As the FPR32 and FPR64 registers have the same names, use validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an FPR64 when necessary. The rest of this patch is very similar to the RV32F patch. Differential Revision: https://reviews.llvm.org/D39895 llvm-svn: 320023
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+36
| | | | | | | | | | | | | The most interesting part of this patch is probably the handling of rounding mode arguments. Sadly, the RISC-V assembler handles floating point rounding modes as a special "argument" when it would be more consistent to handle them like the atomics, opcode suffixes. This patch supports parsing this optional parameter, using InstAlias to allow parsing these floating point instructions when no rounding mode is specified. Differential Revision: https://reviews.llvm.org/D39893 llvm-svn: 320020
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-6/+31
| | | | llvm-svn: 317791
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
| | | | | | | This is necessary to avoid an assertion in the included test case and similar assembler inputs. llvm-svn: 316168
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
| | | | llvm-svn: 316167
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+2
| | | | | | | | | | | | | This adds debug tracing to the table-generated assembly instruction matcher, enabled by the -debug-only=asm-matcher option. The changes in the target AsmParsers are to add an MCInstrInfo reference under a consistent name, so that we can use it from table-generated code. This was already being used this way for targets that use deprecation warnings, but 5 targets did not have it, and Hexagon had it under a different name to the other backends. llvm-svn: 315445
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-20/+162
| | | | | | | | | | | | | %lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-171-11/+145
| | | | | | | | | | This patch supports all RV32I instructions as described in the RISC-V manual. A future patch will add support for pseudoinstructions and other instruction expansions (e.g. 0-arg fence -> fence iorw, iorw). Differential Revision: https://reviews.llvm.org/D23566 llvm-svn: 313485
* [RISCV][NFC] Fix sorting of includes in lib/Target/RISCVAlex Bradbury2017-09-061-5/+5
| | | | llvm-svn: 312624
* [RISCV] Fix warning about unused getSubtargetFeatureName()Alex Bradbury2017-08-081-1/+0
| | | | llvm-svn: 310375
* [RISCV] Add basic RISCVAsmParser (missing files)Alex Bradbury2017-08-081-0/+373
This commit adds the files missing from rL310361. Apologies for the noise. Differential Revision: https://reviews.llvm.org/D23563 llvm-svn: 310363
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