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path: root/llvm/lib/Target/R600/R600Packetizer.cpp
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* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-9/+12
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-5/+5
| | | | | | Remove the old functions. llvm-svn: 202636
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-0/+8
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-101-1/+1
| | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192363
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-121-0/+4
| | | | | | | | | | | | | | | | This fixes some regressions in the piglit local memory store tests introduced by recent commits which made the scheduler aware of the trans slot. It's not possible to test this using lit, because there is no way to determine from the assembly dumps whether or not an instruction is in the trans slot. Even if this were possible, the test would be highly sensitive to changes in the scheduler and might generate confusing false negatives. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 190574
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-5/+33
| | | | llvm-svn: 189980
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-33/+5
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-5/+33
| | | | llvm-svn: 187514
* R600: Don't mix LDS and non-LDS instructions in the same groupVincent Lejeune2013-07-311-0/+4
| | | | | | | | There are a lot of restrictions on instruction groups that contain LDS instructions, so for now we will be conservative and not packetize anything else with them. llvm-svn: 187513
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-1/+2
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-34/+56
| | | | llvm-svn: 185268
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+3
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-1/+7
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-9/+9
| | | | llvm-svn: 184880
* R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune2013-06-031-3/+1
| | | | llvm-svn: 183111
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-12/+9
| | | | | | while there. llvm-svn: 182594
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-1/+2
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Some factorizationVincent Lejeune2013-05-171-138/+11
| | | | llvm-svn: 182123
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-38/+51
| | | | llvm-svn: 180959
* R600: Packetize instructionsVincent Lejeune2013-04-301-0/+446
llvm-svn: 180760
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