summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/R600ISelLowering.cpp
Commit message (Collapse)AuthorAgeFilesLines
* R600: Fix scheduler crash caused by invalid MachinePointerInfoTom Stellard2013-02-191-1/+1
| | | | | | | | | | | | | | Kernel function arguments are lowered to loads from the PARAM_I address space. When creating these load instructions, we were initializing their MachinePointerInfo with an Arguement object that was not attached to any function. This was causing the MachineScheduler to crash when it tried to access the parent of the Arguement. This has been fixed by initializing the MachinePointerInfo with a UndefValue instead. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175517
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-141-62/+50
| | | | | Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
* R600: Add support for SET*_DX10 instructionsTom Stellard2013-02-071-29/+79
| | | | | | | | | | | These instructions compare two floating point values and return an integer true (-1) or false (0) value. When compiling code generated by the Mesa GLSL frontend, the SET*_DX10 instructions save us four instructions for most branch decisions that use floating-point comparisons. llvm-svn: 174609
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-2/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Don't use MRI liveouts in R600.Jakob Stoklund Olesen2013-02-051-4/+11
| | | | | | | | | | | | Something very strange is going on with the output registers in this target. Its ISelLowering code is inserting dangling CopyToReg nodes, hoping that those physregs won't get clobbered before the RETURN. This patch adds the output registers as implicit uses on RETURN instructions in the custom emission pass. I'd much prefer to have those CopyToReg nodes glued to the RETURNs, but I don't see how. llvm-svn: 174400
* R600: improve inputs/interpolation handlingTom Stellard2013-02-051-66/+28
| | | | | | | | | | | | | | | | Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174394
* R600: Consider bitcast when folding const_address node.Tom Stellard2013-01-311-0/+8
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174098
* R600: Add a llvm.R600.store.swizzle intrinsicsTom Stellard2013-01-231-2/+18
| | | | | | | | | | This intrinsic is translated to ALLOC_EXPORT_WORD1_SWIZ, hence its name. It is used to store vs/fs outputs Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173297
* R600: Simplify stream outputs intrinsicTom Stellard2013-01-231-32/+0
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173296
* R600: rework handling of the constantsTom Stellard2013-01-231-9/+113
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-2/+2
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* R600: Expand vec4 INT <-> FP conversionsTom Stellard2012-12-211-0/+4
| | | | llvm-svn: 170901
* Fix warnings with -DNDEBUGTom Stellard2012-12-131-1/+1
| | | | | | Patch by: NAKAMURA Takumi llvm-svn: 170142
* Add R600 backendTom Stellard2012-12-111-0/+905
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
OpenPOWER on IntegriCloud