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path: root/llvm/lib/Target/R600/R600ControlFlowFinalizer.cpp
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* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-3/+2
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600: Make ShaderType privateMatt Arsenault2014-07-131-2/+2
| | | | llvm-svn: 212896
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
| | | | llvm-svn: 210869
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-2/+2
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-4/+4
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* R600: Correctly handle vertex fetch clauses the precede ENDIFsTom Stellard2014-01-231-0/+1
| | | | | | | | The control flow finalizer would sometimes use an ALU_POP_AFTER instruction before the vetex fetch clause instead of using a POP instruction after it. llvm-svn: 199917
* R600: Recommit 199842: Add work-around for the CF stack entry HW bugTom Stellard2014-01-231-1/+42
| | | | | | | | | | | | | | | | | | The unit test is now disabled on non-asserts builds. The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199905
* Revert "R600: Add work-around for the CF stack entry HW bug"Tom Stellard2014-01-221-42/+1
| | | | | | | | | This reverts commit 35b8331cad6eb512a2506adbc394201181da94ba. The -debug-only flag for llc doesn't appear to be available in all build configurations. llvm-svn: 199845
* R600: Add work-around for the CF stack entry HW bugTom Stellard2014-01-221-1/+42
| | | | | | | | | | | | | | | | The CF stack can be corrupted if you use CF_ALU_PUSH_BEFORE, CF_ALU_ELSE_AFTER, CF_ALU_BREAK, or CF_ALU_CONTINUE when the number of sub-entries on the stack is greater than or equal to the stack entry size and sub-entries modulo 4 is either 0 or 3 (on cedar the bug is present when number of sub-entries module 8 is either 7 or 0) We choose to be conservative and always apply the work-around when the number of sub-enries is greater than or equal to the stack entry size, so that we can safely over-allocate the stack when we are unsure of the stack allocation rules. reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199842
* R600: Refactor stack size calculationTom Stellard2014-01-221-36/+139
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199840
* R600: CF_PUSH is the same on Evergreen and CaymanTom Stellard2014-01-221-1/+1
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199839
* R600: Workaround for cayman loop bugVincent Lejeune2013-12-021-0/+10
| | | | llvm-svn: 196121
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-9/+4
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188516
* R600: Change the RAT instruction assembly names so they match the docsTom Stellard2013-08-161-2/+2
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188515
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-1/+3
| | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> llvm-svn: 187582
* R600: Remove predicated_break instVincent Lejeune2013-07-311-9/+2
| | | | | | | | | | | | | We were using two instructions for similar purpose : break and predicated break. Only predicated_break was emitted and it was lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP. This commit simplify the situation by making AMDILCFGStructurizer emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which is now removed). There is no functionality change. llvm-svn: 187510
* R600: Don't emit empty then clause and use alu_pop_afterVincent Lejeune2013-07-191-9/+39
| | | | llvm-svn: 186725
* Make some arrays 'static const'Craig Topper2013-07-151-1/+1
| | | | llvm-svn: 186307
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-0/+2
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-141-0/+1
| | | | | | | | | We were using RAT_INST_STORE_RAW, which seemed to work, but the docs say this instruction doesn't exist for Cayman, so it's probably safer to use a documented instruction instead. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184015
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-6/+4
| | | | llvm-svn: 183592
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-6/+8
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-7/+9
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: CALL_FS consumes a stack size entryVincent Lejeune2013-06-031-0/+1
| | | | llvm-svn: 183108
* R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard2013-05-231-2/+9
| | | | | | | | | Patch by: Vincent Lejeune https://bugs.freedesktop.org/show_bug.cgi?id=64877 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182600
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-4/+5
| | | | | | while there. llvm-svn: 182594
* Setting the default value (fixes CRT assertions about uninitialized variable ↵Aaron Ballman2013-05-231-3/+3
| | | | | | use when doing debug MSVC builds), and fixing coding style. llvm-svn: 182585
* R600: Some factorizationVincent Lejeune2013-05-171-9/+7
| | | | llvm-svn: 182123
* R600: Factorize Fetch size limit inside AMDGPUSubTargetVincent Lejeune2013-05-171-5/+2
| | | | llvm-svn: 182122
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-3/+3
| | | | llvm-svn: 180960
* R600: use native for aluVincent Lejeune2013-04-301-1/+109
| | | | llvm-svn: 180761
* R600: Take inner dependency into tex/vtx clausesVincent Lejeune2013-04-301-0/+34
| | | | llvm-svn: 180757
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-301-10/+31
| | | | llvm-svn: 180756
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-301-36/+9
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard2013-04-291-1/+1
| | | | llvm-svn: 180735
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-231-5/+21
| | | | llvm-svn: 180124
* R600: Add CF_ENDVincent Lejeune2013-04-231-42/+49
| | | | llvm-svn: 180123
* R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-04-111-0/+1
| | | | llvm-svn: 179263
* Whitespace.NAKAMURA Takumi2013-04-111-2/+1
| | | | llvm-svn: 179262
* R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune2013-04-101-1/+10
| | | | llvm-svn: 179174
* R600: Control Flow support for pre EG genVincent Lejeune2013-04-081-12/+72
| | | | llvm-svn: 179020
* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-041-1/+1
| | | | llvm-svn: 178762
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-041-0/+4
| | | | llvm-svn: 178761
* R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizerVincent Lejeune2013-04-031-20/+21
| | | | llvm-svn: 178665
* R600: Consider KILLGT as an ALU instructionVincent Lejeune2013-04-031-1/+0
| | | | | | | Mesa does not override llvm behavior wrt KILLGT anymore so llvm has to handle KILLGT on its own. llvm-svn: 178664
* R600: Add support for native control flowVincent Lejeune2013-04-011-0/+264
llvm-svn: 178505
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