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* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-141-1/+3
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184016
* R600: Hide symbols of implementation details.Benjamin Kramer2013-05-231-0/+4
| | | | | | Also removes an unused function. llvm-svn: 182587
* Fix 32 bit build in c++11 mode.Rafael Espindola2013-05-231-1/+1
| | | | | | | | The error was: error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing] MI.getOperand(6).getImm() & 0x1F, llvm-svn: 182584
* s/u_int32_t/uint32_t/Rafael Espindola2013-05-221-2/+2
| | | | llvm-svn: 182444
* Fix the build in c++11 mode.Rafael Espindola2013-05-171-2/+2
| | | | | | | | | | | | The errors were: non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list and non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list llvm-svn: 182168
* R600: Improve texture handlingVincent Lejeune2013-05-171-72/+23
| | | | llvm-svn: 182125
* R600: Fix encoding for R600 family GPUsTom Stellard2013-05-171-0/+7
| | | | | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64193 https://bugs.freedesktop.org/show_bug.cgi?id=64257 https://bugs.freedesktop.org/show_bug.cgi?id=64320 NOTE: This is a candidate for the 3.3 branch. llvm-svn: 182113
* R600: Pass MCSubtargetInfo reference to R600CodeEmitterTom Stellard2013-05-173-6/+10
| | | | llvm-svn: 182112
* Remove unused fields and arguments.Rafael Espindola2013-05-133-13/+6
| | | | llvm-svn: 181706
* Fix the R600 build.Rafael Espindola2013-05-102-3/+2
| | | | llvm-svn: 181621
* R600: Remove dead code from the CodeEmitter v2Tom Stellard2013-05-061-397/+59
| | | | | | | | | v2: - Replace switch statement with TSFlags query Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181229
* R600: Stop emitting the instruction type byte before each instructionTom Stellard2013-05-061-33/+2
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181225
* R600: Emit ISA for CALL_FS_* instructionsTom Stellard2013-05-061-1/+0
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181223
* R600: use native for aluVincent Lejeune2013-04-301-2/+5
| | | | llvm-svn: 180761
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-301-1/+1
| | | | llvm-svn: 180758
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-301-5/+11
| | | | llvm-svn: 180756
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-231-4/+0
| | | | llvm-svn: 180124
* R600: Add CF_ENDVincent Lejeune2013-04-231-1/+5
| | | | llvm-svn: 180123
* Remove unused DwarfSectionOffsetDirective stringMatt Arsenault2013-04-221-2/+0
| | | | | | | The value isn't actually used, and setting it emits a COFF specific directive. llvm-svn: 180064
* R600: Export is emitted as a CF_NATIVE instVincent Lejeune2013-04-171-10/+5
| | | | llvm-svn: 179685
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | llvm-svn: 179544
* R600: Control Flow support for pre EG genVincent Lejeune2013-04-081-10/+20
| | | | llvm-svn: 179020
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
| | | | llvm-svn: 178763
* R600: Add support for native control flowVincent Lejeune2013-04-011-1/+20
| | | | llvm-svn: 178505
* R600: Emit CF_ALU and use true kcache register.Vincent Lejeune2013-04-011-1/+9
| | | | llvm-svn: 178503
* R600: Emit native instructions for texVincent Lejeune2013-03-311-98/+72
| | | | llvm-svn: 178452
* These two are default in the constructor for MCAsmInfo.Eric Christopher2013-03-281-2/+0
| | | | llvm-svn: 178293
* R600/SIMCCodeEmitter.cpp: Prune a couple of unused members, STI and Ctx. ↵NAKAMURA Takumi2013-03-261-3/+1
| | | | | | [-Wunused-private-field] llvm-svn: 178065
* R600/SI: remove GPR*AlignEncodeChristian Konig2013-03-012-41/+0
| | | | | | | It's much easier to specify the encoding with tablegen directly. Signed-off-by: Christian König <christian.koenig@amd.com> llvm-svn: 176344
* R600/SI: fix stupid typoChristian Konig2013-02-261-1/+1
| | | | | | | | This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176097
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-182-4/+4
| | | | | | | Also removes some redundant DNI comments on function declarations already using the macro. llvm-svn: 175466
* R600: Support for TBOVincent Lejeune2013-02-181-1/+2
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175445
* R600/SI: cleanup literal handling v3Christian Konig2013-02-161-21/+125
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: remove some more unused codeChristian Konig2013-02-161-7/+0
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175350
* R600: Add support for 128-bit parametersTom Stellard2013-02-131-0/+1
| | | | | NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175096
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-071-137/+4
| | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174656
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-072-38/+0
| | | | | | | | | | The _SGPR variants where wrong. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174653
* R600: rework handling of the constantsTom Stellard2013-01-231-38/+43
| | | | | | | | | | | | | | | | | | | | Remove Cxxx registers, add new special register - "ALU_CONST" and new operand for each alu src - "sel". ALU_CONST is used to designate that the new operand contains the value to override src.sel, src.kc_bank, src.chan for constants in the driver. Patch by: Vadim Girlin Vincent Lejeune: - Use pointers for constants - Fold CONST_ADDRESS when possible Tom Stellard: - Give CONSTANT_BUFFER_0 its own address space - Use integer types for constant loads Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173222
* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-1/+1
| | | | | | No change in functionality. llvm-svn: 171822
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-023-4/+3
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* R600: BB operand support for SITom Stellard2012-12-172-1/+15
| | | | | | | | | Patch by: Christian König Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de> llvm-svn: 170342
* Add R600 backendTom Stellard2012-12-1111-0/+1341
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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