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* R600: Remove unnecessary build_vector pattern.Matt Arsenault2014-02-261-7/+1
| | | | | | It is already fully handled in AMDGPUISelDAGToDAG. llvm-svn: 202312
* R600: Disable the BFE patternTom Stellard2014-01-231-0/+7
| | | | | | | | | | This pattern uses an SDNodeXForm, which isn't being emitted for some reason. I can get it to work by attaching the PatLeaf that has the XForm to the argument in the output pattern, but this results in an immediate being used in a register operand, which the backend can't handle yet. llvm-svn: 199918
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-221-34/+41
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-0/+4
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* Target/R600: Un-tab-ify.NAKAMURA Takumi2013-10-281-1/+1
| | | | llvm-svn: 193510
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-0/+21
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+5
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+5
| | | | llvm-svn: 190080
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-2/+18
| | | | llvm-svn: 189225
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-5/+15
| | | | llvm-svn: 189223
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-0/+15
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188519
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-141-49/+0
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. llvm-svn: 188427
* R600: Add support for 24-bit MUL instructionsTom Stellard2013-07-231-0/+13
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186922
* R600: Improve support for < 32-bit loadsTom Stellard2013-07-231-2/+18
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186921
* R600: Clean up extended load patternsTom Stellard2013-07-231-2/+18
| | | | | Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186914
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-151-0/+20
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 186339
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+9
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600/SI: Add support for global loadsTom Stellard2013-06-031-0/+4
| | | | llvm-svn: 183131
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-201-0/+6
| | | | | | The hardware supports rotr and not rotl. llvm-svn: 182285
* R600: Remove AMDILPeeopholeOptimizer and replace optimizations with tablegen ↵Tom Stellard2013-05-101-0/+11
| | | | | | | | | | | | | | patterns The BFE optimization was the only one we were actually using, and it was emitting an intrinsic that we don't support. https://bugs.freedesktop.org/show_bug.cgi?id=64201 Reviewed-by: Christian König <christian.koenig@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181580
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-031-0/+8
| | | | | | This can be optimized using the BFI_INT instruction. llvm-svn: 181033
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-021-67/+62
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. llvm-svn: 180922
* R600: Add pattern for the BFI_INT instructionTom Stellard2013-04-191-0/+20
| | | | llvm-svn: 179830
* R600/SI: Add pattern for AMDGPUurecipMichel Danzer2013-04-101-0/+1
| | | | | | | 21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 179186
* R600/SI: add float vector typesChristian Konig2013-03-181-2/+2
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 177276
* R600/SI: remove shader type intrinsicChristian Konig2013-03-071-7/+0
| | | | | | | | Just encode the type as target specific attribute. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176622
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-211-0/+5
| | | | | | | | | | | Fixing asm operation names. v2: fix name of the e64 encoding, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175750
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-071-0/+51
| | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174632
* R600: Consolidate sub register indices.Tom Stellard2013-02-071-2/+2
| | | | | | | | | | Use sub0-15 everywhere. Patch by: Michel Dänzerr Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 174610
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Add R600 backendTom Stellard2012-12-111-0/+190
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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