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path: root/llvm/lib/Target/R600/AMDGPUIndirectAddressing.cpp
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* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+3
| | | | | | | | the internals of TargetMachine could change. No functionality change intended. llvm-svn: 183561
* R600: Don't compare iterators of different maps.Benjamin Kramer2013-06-071-1/+1
| | | | | | Found be libstdc's debug mode. llvm-svn: 183549
* R600/SI: fix unused variable warningChristian Konig2013-03-071-1/+0
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176620
* R600: Fix tracking of implicit defs in the IndirectAddressing passTom Stellard2013-02-191-7/+25
| | | | | | | | | In some cases, we were losing track of live implicit registers which was creating dead defs and causing the scheduler to produce invalid code. NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175516
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+326
Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
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