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* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+23
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-251-0/+22
| | | | | | | | | | By default, we expand these operations for both EG and SI. Move the duplicated code into a common space for now. If the targets ever actually implement these operations as instructions, we can override that in the relevant target. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184848
* R600/SI: Add a calling convention for compute shadersTom Stellard2013-06-031-0/+2
| | | | llvm-svn: 183137
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-6/+6
| | | | | | | Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. llvm-svn: 182703
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-1/+1
| | | | | | while there. llvm-svn: 182594
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-201-0/+3
| | | | | | The hardware supports rotr and not rotl. llvm-svn: 182285
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-271-0/+2
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 178126
* R600/SI: add proper formal parameter handling for SIChristian Konig2013-03-071-11/+9
| | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176623
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-181-7/+3
| | | | llvm-svn: 175446
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* R600: improve inputs/interpolation handlingTom Stellard2013-02-051-2/+0
| | | | | | | | | | | | | | | | Use one intrinsic for all sorts of interpolation. Use two separate unexpanded instructions to represent INTERP_XY and _ZW - this will allow to eliminate one part if it's not used. Track liveness of special interpolation regs instead of reserving them - this will allow to reuse those regs, lowering reg pressure. Patch By: Vadim Girlin v2[Vincent Lejeune]: Rebased against current llvm master Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174394
* R600: Add a CONST_ADDRESS node to model constant buf readTom Stellard2013-01-231-0/+1
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 173221
* Add R600 backendTom Stellard2012-12-111-0/+417
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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