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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-0/+84
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* Use .data() instead of &x[0]Matt Arsenault2014-04-071-9/+10
| | | | llvm-svn: 205722
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-311-0/+24
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-311-0/+2
| | | | llvm-svn: 205235
* R600: Implement isZExtFree.Matt Arsenault2014-03-271-0/+16
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-0/+18
| | | | llvm-svn: 204945
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cppMatt Arsenault2014-03-251-0/+9
| | | | | | | | Remove handling of select_cc, since it makes no sense to be there. This now does nothing, but I'll be adding some handling of other target nodes soon. llvm-svn: 204743
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-241-0/+10
| | | | llvm-svn: 204658
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-0/+111
| | | | llvm-svn: 204072
* R600: Remove unnecessary attempt to zext a pointer.Matt Arsenault2014-03-151-3/+6
| | | | | | Private pointers are now always 32-bits. llvm-svn: 203989
* R600: Code cleanup.Matt Arsenault2014-03-151-11/+12
| | | | | | | Use sign_extend_inreg and getZeroExtendInReg instead of using the bit operations they expand into. llvm-svn: 203988
* R600: Fix trunc store from i64 to i1Matt Arsenault2014-03-121-0/+6
| | | | llvm-svn: 203695
* R600: Calculate store mask instead of using switch.Matt Arsenault2014-03-111-17/+3
| | | | llvm-svn: 203527
* Use .data() instead of &x[0]Matt Arsenault2014-03-111-2/+2
| | | | llvm-svn: 203516
* R600: Fix extloads from i8 / i16 to i64.Matt Arsenault2014-03-061-2/+14
| | | | | | | This appears to only be working for global loads. Private and local break for other reasons. llvm-svn: 203135
* R600/SI: Expand selects on vectors.Matt Arsenault2014-03-061-0/+2
| | | | llvm-svn: 203134
* Fix typoMatt Arsenault2014-03-051-3/+3
| | | | llvm-svn: 203013
* R600/SI - Add new CI arithmetic instructions.Matt Arsenault2014-02-241-0/+2
| | | | | | | Does not yet include larger part required to match v_mad_i64_i32 / v_mad_u64_u32. llvm-svn: 202077
* Fix DOT4 missing from getTargetOpcodeNameMatt Arsenault2014-02-241-0/+1
| | | | llvm-svn: 202075
* R600/SI: Expand all v8[if]32 operationsTom Stellard2014-02-131-1/+7
| | | | llvm-svn: 201371
* R600: Always implement both versions of isTruncateFree and add a sanity check.Benjamin Kramer2014-02-121-2/+8
| | | | llvm-svn: 201222
* R600: Implement isTruncateFreeMatt Arsenault2014-02-101-0/+5
| | | | | | | Truncation is just accessing a subregister for any multiple of the register size, so it's free. llvm-svn: 201107
* R600/SI: Expand i1 BR_CCTom Stellard2014-02-041-0/+2
| | | | | | | | | | | This fixes a crashes in the OpenCV test suite and also the scrypt kernel in bfgminer. I was unable to come up with a reduced test case for this. https://bugs.freedesktop.org/show_bug.cgi?id=72785 llvm-svn: 200776
* R600: Enable vector fpow.Tom Stellard2014-02-041-0/+1
| | | | | | | | | | | The OpenCL specs say: "The vector versions of the math functions operate component-wise. The description is per-component." Patch by: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 200773
* R600: Add support for global addresses with constant initializersTom Stellard2014-01-221-15/+103
| | | | llvm-svn: 199825
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-221-0/+78
| | | | llvm-svn: 199823
* R600: Allow ftruncTom Stellard2013-12-201-0/+2
| | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 197783
* Don't manually calculate size in bytesMatt Arsenault2013-12-141-2/+3
| | | | llvm-svn: 197327
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-4/+4
| | | | llvm-svn: 196971
* R600: Expand vector FABSTom Stellard2013-11-271-0/+1
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195881
* R600: Add support for ISD::FROUNDTom Stellard2013-11-271-0/+1
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195878
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-151-0/+12
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. llvm-svn: 194783
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-2/+19
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-5/+5
| | | | llvm-svn: 194153
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-301-0/+22
| | | | llvm-svn: 193701
* R600: Expand vector FSQRT opsTom Stellard2013-10-291-0/+1
| | | | llvm-svn: 193620
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-231-0/+52
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-0/+1
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-051-4/+10
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. llvm-svn: 190078
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+23
| | | | llvm-svn: 189226
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-2/+2
| | | | llvm-svn: 189223
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-53/+99
| | | | llvm-svn: 189222
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-1/+3
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
* R600: Remove unnecessary castsTom Stellard2013-08-211-8/+6
| | | | | | Spotted by Bill Wendling. llvm-svn: 188942
* R600: Expand vector FRINT opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
* R600: Expand vector FFLOOR opsTom Stellard2013-08-161-0/+1
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188597
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-161-4/+18
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188596
* R600: Add support for global vector loads with element types less than 32-bitsTom Stellard2013-08-161-0/+13
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188521
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