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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-5/+20
| | | | | | | | | | | This would assert if a constant address space was extern and therefore didn't have an initializer. If the initializer was undef, it would hit the unreachable unhandled initializer case. An extern global should never really occur since we don't have machine linking, but bugpoint likes to remove initializers. llvm-svn: 210967
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
| | | | llvm-svn: 210966
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-131-9/+31
| | | | | | | | | | | | Move / delete some of the more obviously wrong setOperationAction calls. Most of these are setting Expand for types that aren't legal which is the default anyway. Leave stuff that might require more thought on whether it's junk or not as it is. No functionality change. llvm-svn: 210922
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-131-3/+7
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-11/+15
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-111-1/+16
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* Try to fix the msvc build.Rafael Espindola2014-06-111-1/+2
| | | | llvm-svn: 210636
* Use cast instead of assert + dyn_castMatt Arsenault2014-06-111-3/+2
| | | | llvm-svn: 210628
* R600: Add helper functions.Matt Arsenault2014-06-111-0/+19
| | | | | | | Extract these from some of my other patches, since this is the only thing really making them dependent on each other. llvm-svn: 210627
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-101-2/+6
| | | | llvm-svn: 210569
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-1/+11
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-101-0/+7
| | | | llvm-svn: 210564
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+1
| | | | llvm-svn: 210475
* R600: Set all float vector expands in the same placeMatt Arsenault2014-06-011-5/+2
| | | | llvm-svn: 209988
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-221-0/+21
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-221-0/+74
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+25
| | | | llvm-svn: 209460
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
| | | | llvm-svn: 209459
* R600: Add intrinsics for mad24Matt Arsenault2014-05-221-0/+10
| | | | llvm-svn: 209456
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
| | | | llvm-svn: 209333
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-211-6/+33
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
| | | | llvm-svn: 209310
* Use range forMatt Arsenault2014-05-151-6/+2
| | | | llvm-svn: 208922
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-14/+14
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-121-0/+8
| | | | llvm-svn: 208604
* Fix return before elseMatt Arsenault2014-05-111-18/+18
| | | | llvm-svn: 208510
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+2
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-9/+13
| | | | llvm-svn: 208429
* R600: Promote f64 vector load/stores to i64 for consistencyMatt Arsenault2014-05-081-0/+6
| | | | llvm-svn: 208344
* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-0/+1
| | | | llvm-svn: 208005
* R600: Expand vector sin and cos.Tom Stellard2014-05-021-0/+2
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+2
| | | | llvm-svn: 207844
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-22/+44
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* R600: Implement iterative algorithm for udivremTom Stellard2014-04-291-0/+50
| | | | | | | | | | Initial implementation, rather slow Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207588
* R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard2014-04-291-1/+19
| | | | | | | | | | | | | | | | | | When legalizing ops, with UDIV/UREM set to expand, they automatically expand to UDIVREM (if legal or custom). We need to do this manually for legalize types. v2: SI should be set to Expand because the type is legal, and it is automatically lowered to UDIVREM if UDIVREM is Legal/Custom R600 should set to UDIV/UREM to Custom because it needs to lower them during type legalization Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207587
* R600: remove unused variableTom Stellard2014-04-291-2/+0
| | | | | | | | Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207586
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207397
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-1/+1
| | | | llvm-svn: 207374
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-10/+6
| | | | llvm-svn: 207327
* R600: Fix function name printing in LowerCallMatt Arsenault2014-04-251-1/+3
| | | | | | | | v2: Check both ExternalSymbol and GlobalAddress Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207282
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
| | | | llvm-svn: 207197
* R600: Emit error instead of unreachable on function callMatt Arsenault2014-04-221-0/+59
| | | | llvm-svn: 206904
* R600: Change how vector truncating stores are packed.Matt Arsenault2014-04-221-11/+25
| | | | | | | Don't introduce new operations on an illegal sub 32-bit type. Do the operations on a 32-bit value, and then use a truncating store. llvm-svn: 206864
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-70/+11
| | | | | | Don't know why I didn't just do this in the first place. llvm-svn: 206862
* R600: Add comment clariying use of sext for result of MUL_U24Tom Stellard2014-04-171-0/+2
| | | | llvm-svn: 206501
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-161-16/+0
| | | | | | | | | | | | | | Setting vector types to expand will result in scalarization on pre SI hw, as those gpus don't have vector shifts either. Expand also i32 vectors, this helps llvm make the correct decision about scalarizing the vector ops. v2: move setOperation() calls to R600ISelLowering.cpp. cleanup the SI code to make it obvious that this patch does is nop for SI Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 206348
* R600/SI: Fix loads of i1Matt Arsenault2014-04-151-0/+14
| | | | llvm-svn: 206330
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of ↵Nick Lewycky2014-04-151-1/+2
| | | | | | its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. llvm-svn: 206255
* Move ExtractVectorElements to SelectionDAG.Matt Arsenault2014-04-111-20/+6
| | | | | | | This seems generally useful, and makes sense to go along with SplitVector. llvm-svn: 206041
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