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path: root/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
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* R600: Implement zero undef variants of ctlz/cttzJan Vesely2014-07-151-0/+6
* R600: Add dag combine for copy of an illegal type.Matt Arsenault2014-07-151-1/+55
* R600: Implement float to long/ulongJan Vesely2014-07-101-1/+0
* R600: Fix mishandling of load / store chains.Matt Arsenault2014-07-071-11/+49
* R600: Add a comment that llvm.AMDGPU.trunc is a legacy intrinsicTom Stellard2014-07-021-1/+1
* R600: Promote i64 loads to v2i32Tom Stellard2014-07-021-0/+3
* R600: Fix crashes when an illegal type load or store is not handled.Matt Arsenault2014-07-021-2/+6
* R600: Move mul combine to separate functionMatt Arsenault2014-06-301-28/+33
* R600: Move load/store ReplaceNodeResults to common code.Matt Arsenault2014-06-271-0/+14
* Silencing a warning about isZExtFree hiding an inherited virtual function. No...Aaron Ballman2014-06-261-0/+4
* R600: Fix vector FMAMatt Arsenault2014-06-261-0/+1
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-241-0/+3
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-241-0/+8
* R600: Remove DIV_INFMatt Arsenault2014-06-241-2/+2
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-2/+14
* R600: Remove AMDILISelLoweringMatt Arsenault2014-06-231-7/+0
* R600: Select is not expensive.Matt Arsenault2014-06-231-0/+7
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+4
* R600: Move more out of AMDILISelLoweringMatt Arsenault2014-06-231-0/+13
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-1/+0
* R600: Rename AMDIL fileMatt Arsenault2014-06-231-1/+1
* R600: Use LowerSDIVREM for i64 node replaceJan Vesely2014-06-221-90/+0
* R600: Implement custom SDIVREM.Jan Vesely2014-06-221-4/+43
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-0/+2
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+1
* R600: Expand vector fexp2Tom Stellard2014-06-201-0/+1
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-191-2/+30
* Use stdint macros for specifying size of constantsMatt Arsenault2014-06-181-2/+3
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+12
* Use LL suffix for literal that should be 64-bits.Matt Arsenault2014-06-181-1/+1
* R600: Expand vector fceilJan Vesely2014-06-181-0/+1
* Work around ridiculous warning.Matt Arsenault2014-06-181-2/+5
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+4
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-181-0/+107
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-181-0/+26
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+2
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+1
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+1
* Fix copy paste errorMatt Arsenault2014-06-151-1/+1
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-151-19/+21
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-4/+4
* R600: Move / cleanup more leftover AMDIL stuff.Matt Arsenault2014-06-151-5/+19
* R600: Move division custom lowering out of AMDILISelLoweringMatt Arsenault2014-06-151-2/+246
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-0/+7
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-5/+20
* R600: Use address space enum instead of valueMatt Arsenault2014-06-141-6/+7
* R600: Cleanup some old AMDIL stuff.Matt Arsenault2014-06-131-9/+31
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-131-3/+7
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-11/+15
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-111-1/+16
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