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path: root/llvm/lib/Target/R600/AMDGPUAsmPrinter.cpp
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* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-0/+1
| | | | llvm-svn: 210869
* R600/SI: Print code size along with used registersMatt Arsenault2014-04-151-12/+13
| | | | llvm-svn: 206336
* R600/SI: Use correct dest register class for V_READFIRSTLANE_B32Tom Stellard2014-03-171-1/+2
| | | | | | | | | | | | This instructions writes to an 32-bit SGPR. This change required adding the 32-bit VCC_LO and VCC_HI registers, because the full VCC register is 64 bits. This fixes verifier errors on several of the indirect addressing piglit tests. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 204055
* Remove MCPureStreamer.Rafael Espindola2014-02-271-2/+0
| | | | | | | We moved MCJIT to use native object formats a long time ago and R600 now uses ELF, so it was dead. llvm-svn: 202408
* Remove the last hasRawTextSupport call from R600.Rafael Espindola2014-01-311-2/+1
| | | | | | | | There is nothing wrong with printing the disassembly section when printing text. An hypothetical assembler would then produce a .o just like our direct object emission produces. llvm-svn: 200583
* Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.Rafael Espindola2014-01-311-2/+2
| | | | llvm-svn: 200582
* Use emitRawComment to avoid a call to hasRawTextSupport.Rafael Espindola2014-01-311-3/+1
| | | | llvm-svn: 200581
* Add back spaces I missed in the conversion to emitRawComments.Rafael Espindola2014-01-271-3/+3
| | | | | | Sorry about that. llvm-svn: 200171
* Use emitRawComment instead of EmitRawText.Rafael Espindola2014-01-271-4/+5
| | | | llvm-svn: 200170
* R600: Add stack size to .AMDGPUcsdata sectionTom Stellard2014-01-221-4/+10
| | | | | reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 199837
* Move declaration of variables down to first use.Matt Arsenault2014-01-081-6/+4
| | | | llvm-svn: 198794
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-1/+1
| | | | llvm-svn: 196971
* R600/SI: Add comments for number of used registers.Matt Arsenault2013-12-051-9/+41
| | | | llvm-svn: 196467
* Indentation fixesMatt Arsenault2013-11-141-1/+1
| | | | llvm-svn: 194688
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-291-2/+14
| | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-0/+3
| | | | llvm-svn: 193212
* R600/SI: Don't assert on SCC usageMatt Arsenault2013-10-221-0/+2
| | | | llvm-svn: 193198
* R600: Store disassembly in a special ELF section when feature +DumpCode is ↵Tom Stellard2013-10-121-8/+36
| | | | | | | | | enabled. Patch by: Jay Cornwall Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 192523
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+7
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+6
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-2/+2
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* Move passes from namespace llvm into anonymous namespaces. Sort includes ↵Benjamin Kramer2013-05-231-3/+3
| | | | | | while there. llvm-svn: 182594
* R600: Emit config values in register / value pairsTom Stellard2013-05-061-3/+29
| | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 181228
* R600: config section now reports use of killgtVincent Lejeune2013-04-301-0/+4
| | | | llvm-svn: 180751
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-241-1/+1
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. llvm-svn: 180230
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-231-0/+3
| | | | llvm-svn: 180124
* R600: Emit used GPRs countVincent Lejeune2013-04-171-7/+39
| | | | llvm-svn: 179684
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-151-3/+16
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. llvm-svn: 179546
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | llvm-svn: 179545
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-101-0/+3
| | | | | | | | Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 179166
* R600/SI: rework input interpolation v2Christian Konig2013-03-071-1/+1
| | | | | | | | v2: update CMakeLists.txt as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 176626
* R600/SI: cleanup literal handling v3Christian Konig2013-02-161-2/+0
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-071-1/+1
| | | | | | | | | | Remove all the unused code. Patch by: Christian König Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174656
* R600/SI: Add basic support for more integer vector types.Tom Stellard2013-02-071-0/+6
| | | | | | | | | | | | | v1i32, v2i32, v8i32 and v16i32. Only add VGPR register classes for integer vector types, to avoid attempts copying from VGPR to SGPR registers, which is not possible. Patch By: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174632
* R600: Emit function name in the AsmPrinterTom Stellard2013-02-051-0/+3
| | | | | | | | Emitting the function name allows us to check for it in the FileCheck tests so we can make sure FileCheck is checking the output of the correct function. llvm-svn: 174392
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Add R600 backendTom Stellard2012-12-111-0/+138
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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