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* fix formatting issue; NFCHiroshi Inoue2017-07-181-4/+6
| | | | llvm-svn: 308305
* Add a set of comments explaining why getSubtargetImpl() is deleted on these ↵Eric Christopher2017-07-141-0/+2
| | | | | | targets. llvm-svn: 307999
* [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16Nemanja Ivanovic2017-07-137-67/+126
| | | | | | | | | | | | | As outlined in the PR, we didn't ensure that displacements for DQ-Form instructions are multiples of 16. Since the instruction encoding encodes a quad-word displacement, a sub-16 byte displacement is meaningless and ends up being encoded incorrectly. Fixes https://bugs.llvm.org/show_bug.cgi?id=33671. Differential Revision: https://reviews.llvm.org/D35007 llvm-svn: 307934
* Fully fix the movw/movt addend.Rafael Espindola2017-07-111-1/+1
| | | | | | | | | | The issue is not if the value is pcrel. It is whether we have a relocation or not. If we have a relocation, the static linker will select the upper bits. If we don't have a relocation, we have to do it. llvm-svn: 307730
* [PPC] Fix two bugs in frame lowering.Tony Jiang2017-07-112-17/+26
| | | | | | | | | | | 1. The available program storage region of the red zone to compilers is 288 bytes rather than 244 bytes. 2. The formula for negative number alignment calculation should be y = x & ~(n-1) rather than y = (x + (n-1)) & ~(n-1). Differential Revision: https://reviews.llvm.org/D34337 llvm-svn: 307672
* fix formatting; NFCHiroshi Inoue2017-07-111-2/+2
| | | | llvm-svn: 307662
* [PowerPC] fix latency for simple integer instructions in POWER9 schedulerHiroshi Inoue2017-07-111-1/+1
| | | | | | | | | In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions. This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion. Differential Revision: https://reviews.llvm.org/D34869 llvm-svn: 307624
* [PowerPC] avoid redundant analysis while lowering an immediate; NFCHiroshi Inoue2017-07-111-2/+8
| | | | | | | | | | This patch reduces compilation time by avoiding redundant analysis while selecting instructions to create an immediate. If the instruction count required to create the input number without rotate is 2, we do not need further analysis to find a shorter instruction sequence with rotate; rotate + load constant cannot be done by 1 instruction (i.e. getInt64CountDirectnever return 0). This patch should not change functionality. Differential Revision: https://reviews.llvm.org/D34986 llvm-svn: 307623
* [PPC CodeGen] Expand the bitreverse.i64 intrinsic.Tony Jiang2017-07-102-0/+120
| | | | | | | Differential Revision: https://reviews.llvm.org/D34908 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307563
* [PowerPC] Reduce register pressure by not materializing a constant just for ↵Lei Huang2017-07-101-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | use as an index register for X-Form loads/stores. For this example: float test (int *arr) { return arr[2]; } We currently generate the following code: li r4, 8 lxsiwax f0, r3, r4 xscvsxdsp f1, f0 With this patch, we will now generate: addi r3, r3, 8 lxsiwax f0, 0, r3 xscvsxdsp f1, f0 Originally reported in: https://bugs.llvm.org/show_bug.cgi?id=27204 Differential Revision: https://reviews.llvm.org/D35027 llvm-svn: 307553
* fix typos in comments and error messages; NFCHiroshi Inoue2017-07-101-3/+3
| | | | llvm-svn: 307533
* fix formatting; NFCHiroshi Inoue2017-07-101-2/+2
| | | | llvm-svn: 307523
* [PowerPC] NFC : Common up definitions of isIntS16Immediate and update ↵Lei Huang2017-07-073-30/+14
| | | | | | parameter to int16_t llvm-svn: 307442
* [PPC CodeGen] Expand the bitreverse.i32 intrinsic.Tony Jiang2017-07-072-0/+71
| | | | | | | Differential Revision: https://reviews.llvm.org/D33572 Fix PR: https://bugs.llvm.org/show_bug.cgi?id=33093 llvm-svn: 307413
* [PowerPC] Fix -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim2017-07-071-0/+4
| | | | llvm-svn: 307382
* [Power9] Disable removing extra swaps on P9.Sean Fertile2017-07-051-1/+3
| | | | | | | | | | | | On power 8 we sometimes insert swaps to deal with the difference between Little-Endian and Big-Endian. The swap removal pass is supposed to clean up these swaps. On power 9 we don't need this pass since we do not need to insert the swaps in the first place. Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34627 llvm-svn: 307185
* [PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.Sean Fertile2017-07-051-1/+4
| | | | | | | Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D34829 llvm-svn: 307180
* [Power9] Exploit vector extract with variable index.Tony Jiang2017-07-051-0/+92
| | | | | | | | | | | | | | | | This patch adds the exploitation for new power 9 instructions which extract variable elements from vectors: VEXTUBLX VEXTUBRX VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX Differential Revision: https://reviews.llvm.org/D34032 Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) llvm-svn: 307174
* [Power9] Exploit vector integer extend instructions when indices aren't correct.Tony Jiang2017-07-054-26/+216
| | | | | | | | | | | | | | | This patch adds on to the exploitation added by https://reviews.llvm.org/D33510. This now catches build vector nodes where the inputs are coming from sign extended vector extract elements where the indices used by the vector extract are not correct. We can still use the new hardware instructions by adding a shuffle to move the elements to the correct indices. I introduced a new PPCISD node here because adding a vector_shuffle and changing the elements of the vector_extracts was getting undone by another DAG combine. Commit on behalf of Zaara Syeda (syzaara@ca.ibm.com) Differential Revision: https://reviews.llvm.org/D34009 llvm-svn: 307169
* [PowerPC] Fix for PR33636Nemanja Ivanovic2017-07-051-2/+4
| | | | | | | | Remove casts to a constant when a node can be an undef. Differential Revision: https://reviews.llvm.org/D34808 llvm-svn: 307120
* Rename and adjust processFixupValue.Rafael Espindola2017-06-301-5/+6
| | | | | | | It was not processing any value. All that it ever did was force relocations, so name it shouldForceRelocation. llvm-svn: 306906
* Make 0 argument getSubtargetImpl functions for the X86, AArch64, and PPC ↵Eric Christopher2017-06-301-0/+1
| | | | | | targets deleted so that no one is tempted to use them. llvm-svn: 306864
* To help readability of mightUseCTR pull out the inline asm handling support ↵Eric Christopher2017-06-291-10/+17
| | | | | | into a function. llvm-svn: 306762
* Make the PPCCTRLoops pass depend on being able to access the TargetMachine ↵Eric Christopher2017-06-293-49/+36
| | | | | | and clean up accordingly. llvm-svn: 306761
* [PowerPC] fix potential verification error on __tls_get_addrHiroshi Inoue2017-06-293-4/+22
| | | | | | | | | | This patch fixes a verification error with -verify-machineinstrs while expanding __tls_get_addr by not creating ADJCALLSTACKUP and ADJCALLSTACKDOWN if there is another ADJCALLSTACKUP in this basic block since nesting ADJCALLSTACKUP/ADJCALLSTACKDOWN is not allowed. Here, ADJCALLSTACKUP and ADJCALLSTACKDOWN are created as a fence for instruction scheduling to avoid _tls_get_addr is scheduled before mflr in the prologue (https://bugs.llvm.org//show_bug.cgi?id=25839). So if another ADJCALLSTACKUP exists before _tls_get_addr, we do not need to create a new ADJCALLSTACKUP. Differential Revision: https://reviews.llvm.org/D34347 llvm-svn: 306678
* Reuse existing variable. NFC.Rafael Espindola2017-06-281-2/+2
| | | | llvm-svn: 306582
* Don't repeat name in comment and format. NFC.Rafael Espindola2017-06-281-19/+15
| | | | llvm-svn: 306568
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-282-3/+4
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34531 llvm-svn: 306554
* [PowerPC] set optimization level in SelectionDAGISelHiroshi Inoue2017-06-273-6/+8
| | | | | | | | | PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level. This patch makes the PowerPC backend set the optimization level correctly. Differential Revision: https://reviews.llvm.org/D34615 llvm-svn: 306367
* Simplify the processFixupValue interface. NFC.Rafael Espindola2017-06-241-4/+2
| | | | llvm-svn: 306202
* Remove redundant argument.Rafael Espindola2017-06-241-1/+1
| | | | llvm-svn: 306189
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-1/+2
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* [PowerPC] fix potential verification errorsHiroshi Inoue2017-06-222-5/+12
| | | | | | This patch fixes trivial mishandling of 32-bit/64-bit instructions that may cause verification errors with -verify-machineinstrs. llvm-svn: 305984
* Use a MutableArrayRef. NFC.Rafael Espindola2017-06-211-1/+1
| | | | llvm-svn: 305968
* [PowerPC] define target hook isReallyTriviallyReMaterializable()Lei Huang2017-06-213-2/+29
| | | | | | | | | | | Define target hook isReallyTriviallyReMaterializable() to explicitly specify PowerPC instructions that are trivially rematerializable. This will allow the MachineLICM pass to accurately identify PPC instructions that should always be hoisted. Differential Revision: https://reviews.llvm.org/D34255 llvm-svn: 305932
* [PowerPC] fix trivial typos in comment, NFCHiroshi Inoue2017-06-201-1/+1
| | | | llvm-svn: 305813
* Rework logic and comment out the default relocation models for PPC.Eric Christopher2017-06-171-10/+13
| | | | llvm-svn: 305630
* Turn a large if block into a smaller early return for clarity.Eric Christopher2017-06-171-11/+10
| | | | llvm-svn: 305629
* Remove the old and unused PPC32 and PPC64TargetMachine classes.Eric Christopher2017-06-172-47/+4
| | | | llvm-svn: 305628
* Remove unused forward declaration.Eric Christopher2017-06-171-1/+0
| | | | llvm-svn: 305627
* Tidy up some calls to getRegister for readability.Eric Christopher2017-06-171-5/+6
| | | | llvm-svn: 305626
* [PPC] Remove isBarrier from CFENCE8's definition.Tim Shen2017-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is my misunderstanding on isBarrier. It's not for memory barriers, but for other control flow purposes. lwsync doesn't have it either. This fixes a simple crash with -verify-machineinstrs like below: define void @Foo() { entry: %tmp = load atomic i64, i64* undef acquire, align 8 unreachable } I deliberately don't want to check in the test, since there is little chance to regress on such a mistake. Such a test adds noise to the code base. I plan to check in first, since it fixes a crash, and the fix is obvious. Reviewers: kbarton, echristo Subscribers: sanjoy, nemanjai, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34314 llvm-svn: 305624
* [MachineLICM] Hoist TOC-based address instructionsLei Huang2017-06-152-0/+15
| | | | | | | | | | | | | | | | | | Add condition for MachineLICM to safely hoist instructions that utilize non constant registers that are reserved. On PPC, global variable access is done through the table of contents (TOC) which is always in register X2. The ABI reserves this register in any functions that have calls or access global variables. A call through a function pointer involves saving, changing and restoring this register around the call and thus MachineLICM does not consider it to be invariant. We can however guarantee the register is preserved across the call and thus is invariant. Differential Revision: https://reviews.llvm.org/D33562 llvm-svn: 305490
* [PowerPC] fix potential verification errors on CFENCE8Hiroshi Inoue2017-06-151-1/+1
| | | | | | | | This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs. Differential Revision: https://reviews.llvm.org/D34208 llvm-svn: 305479
* Test commit - NFC.Lei Huang2017-06-141-1/+1
| | | | | | Modified a comment to confirm commit access functionality. llvm-svn: 305402
* Revert r304907 as it is causing some failures that I cannot reproduce.Nemanja Ivanovic2017-06-141-26/+0
| | | | | | Reverting this until a test case can be provided to aid the investigation. llvm-svn: 305372
* Test commit - NFC.Kit Barton2017-06-131-1/+1
| | | | | | Modified a comment to confirm commit access functionality. llvm-svn: 305309
* PPCISelLowering.cpp: Fix warnings in r305214. [-Wdocumentation]NAKAMURA Takumi2017-06-131-3/+3
| | | | llvm-svn: 305277
* [PowerPC] Match vec_revb builtins to P9 instructions.Tony Jiang2017-06-124-7/+105
| | | | | | | | | | | | Power9 has instructions that will reverse the bytes within an element for all sizes (half-word, word, double-word and quad-word). These can be used for the vec_revb builtins in altivec.h. However, we implement these to match vector shuffle nodes as that will cover both the builtins and vector shuffles that occur in the SDAG through other means. Differential Revision: https://reviews.llvm.org/D33690 llvm-svn: 305214
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-124-5/+51
| | | | | | | | | | | Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction. Commit on behalf of STEFAN PINTILIE. Differential Revision: https://reviews.llvm.org/D33940 llvm-svn: 305210
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