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* Use indirect calls in PowerPC JIT.Torok Edwin2010-08-043-10/+31
| | | | | | | | | See PR5201. There is no way to know if direct calls will be within the allowed range for BL. Hence emit all calls as indirect when in JIT mode. Without this long-running applications will fail to JIT on PowerPC with a relocation failure. llvm-svn: 110246
* PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.Eli Friedman2010-08-021-3/+3
| | | | llvm-svn: 109998
* PPC doesn't supported VLA with large alignment. This wasDale Johannesen2010-07-301-2/+2
| | | | | | | | formerly rejected by the FE, so asserted in the BE; now the FE only warns, so we treat it as a legitimate fatal error in PPC BE. This means the test for the feature won't pass, so it's xfail'd. llvm-svn: 109892
* fix constness warningsGabor Greif2010-07-231-1/+2
| | | | llvm-svn: 109224
* eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner2010-07-221-1/+1
| | | | | | | | ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. llvm-svn: 109171
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-67/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-163-4/+4
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Emit COPY instead of FMR/FMSD instructions for floating point conversion onJakob Stoklund Olesen2010-07-162-12/+9
| | | | | | PowerPC. llvm-svn: 108555
* Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memoryJakob Stoklund Olesen2010-07-161-0/+19
| | | | | | | | | operands. Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't since missing memoperands should not affect correctness. llvm-svn: 108540
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-132/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for PowerPC.Jakob Stoklund Olesen2010-07-112-36/+30
| | | | llvm-svn: 108083
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-071-1/+1
| | | | | | for consistency sake. llvm-svn: 107820
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-11/+20
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-4/+5
| | | | llvm-svn: 107710
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-17/+29
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Revert r107655.Dan Gohman2010-07-061-29/+17
| | | | llvm-svn: 107668
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-17/+29
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-032-19/+13
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove initialized but otherwise unused variables.Duncan Sands2010-06-291-1/+0
| | | | llvm-svn: 107127
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-252-9/+3
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-3/+3
| | | | llvm-svn: 106279
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-8/+8
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+1
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-1/+1
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-1/+1
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-14/+12
| | | | llvm-svn: 105344
* cleanupRafael Espindola2010-06-022-137/+0
| | | | llvm-svn: 105322
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-11/+19
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-4/+4
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. llvm-svn: 104627
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-8/+12
| | | | llvm-svn: 104571
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-1/+1
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices areJakob Stoklund Olesen2010-05-241-0/+7
| | | | | | never used. llvm-svn: 104517
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-221-1/+4
| | | | llvm-svn: 104421
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-205-21/+24
| | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. llvm-svn: 104238
* Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe whatBill Wendling2010-05-141-1/+1
| | | | | | | | | the variable actually tracks. N.B., several back-ends are using "HasCalls" as being synonymous for something that adjusts the stack. This isn't 100% correct and should be looked into. llvm-svn: 103802
* Set isTerminator on TRAP instructions.Dan Gohman2010-05-141-1/+1
| | | | llvm-svn: 103778
* Don't use isBarrier for the PowerPC sync instruction. isBarrier is forDan Gohman2010-05-141-1/+0
| | | | | | control barriers, not memory ordering barriers. llvm-svn: 103777
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-114-4/+13
| | | | | | | | Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-062-5/+4
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-062-4/+8
| | | | llvm-svn: 103193
* No-ops emitted for scheduling don't correspond with anything in theDan Gohman2010-05-051-2/+0
| | | | | | user's source, so don't arbitrarily assign them a debug location. llvm-svn: 103121
* Implement builtin_return_address(x) and builtin_frame_address(x) Dale Johannesen2010-05-031-23/+34
| | | | | | on PPC for x!=0. 7624113. llvm-svn: 102972
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-012-9/+5
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Make naked functions work on PPC.Dale Johannesen2010-04-291-1/+7
| | | | llvm-svn: 102657
* Frame index can be negative.Evan Cheng2010-04-292-2/+2
| | | | llvm-svn: 102577
* Use MachineOperand::is* predicates.Devang Patel2010-04-271-3/+3
| | | | llvm-svn: 102472
* Add PPC AsmPrinter handling for target-specific form ofDale Johannesen2010-04-261-0/+18
| | | | | | DBG_VALUE, and a cautionary comment. llvm-svn: 102371
* Add PPC specific emitFrameIndexDebugValue.Evan Cheng2010-04-262-0/+16
| | | | llvm-svn: 102325
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