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* Change the names used for internal labels to use the currentDan Gohman2007-10-121-9/+9
| | | | | | | | | function symbol name instead of a codegen-assigned function number. Thanks Evan! :-) llvm-svn: 42908
* Mark vector pow, ctpop, cttz, and ctlz as Expand on PowerPC.Dan Gohman2007-10-121-1/+4
| | | | llvm-svn: 42904
* Set ISD::FPOW to Expand.Dan Gohman2007-10-111-1/+3
| | | | llvm-svn: 42881
* Next PPC long double bits: ppcf128->i32 conversion.Dale Johannesen2007-10-104-1/+179
| | | | | | | Surprisingly complicated. Adds getTargetNode for 2 outputs, no inputs (missing). llvm-svn: 42822
* When we start enabling SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM inDan Gohman2007-10-081-0/+14
| | | | | | target-indepenent lowering, don't use them on PowerPC. llvm-svn: 42755
* Next powerpc long double bits. Comparisons work,Dale Johannesen2007-10-061-0/+4
| | | | | | although not well, and shortening FP converts. llvm-svn: 42672
* First round of ppc long double. call/return andDale Johannesen2007-10-052-2/+15
| | | | | | | | | basic arithmetic works. Rename RTLIB long double functions to distinguish different flavors of long double; the lib functions have different names, alas. llvm-svn: 42644
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-052-47/+164
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* Use empty() member functions when that's what's being tested for insteadDan Gohman2007-10-031-1/+1
| | | | | | of comparing begin() and end(). llvm-svn: 42585
* TargetAsmInfo::getAddressSize() was incorrect for x86-64 and 64-bit targetsDan Gohman2007-09-271-1/+0
| | | | | | | | other than PPC64. Instead of fixing it, just remove it and fix all the places that use it to use TargetData::getPointerSize() instead, as there aren't very many. Most of the references were in DwarfWriter.cpp. llvm-svn: 42419
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-262-8/+15
| | | | | | Tested with "make check"! llvm-svn: 42346
* More explicit keywords.Dan Gohman2007-09-251-3/+3
| | | | llvm-svn: 42316
* Honor user-defined section specification of a global, ignores whether its ↵Evan Cheng2007-09-211-2/+2
| | | | | | initializer is null. llvm-svn: 42182
* Do not override user specified section.Devang Patel2007-09-201-2/+2
| | | | llvm-svn: 42179
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-142-2/+2
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* Fix comments.Evan Cheng2007-09-141-4/+4
| | | | llvm-svn: 41947
* Enable indirect encoding for the personality functionBill Wendling2007-09-111-0/+1
| | | | llvm-svn: 41873
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-112-6/+8
| | | | llvm-svn: 41863
* Fold the adjust_trampoline intrinsic intoDuncan Sands2007-09-111-3/+0
| | | | | | | init_trampoline. There is now only one trampoline intrinsic. llvm-svn: 41841
* Add some notes about better flag handling.Chris Lattner2007-09-101-1/+29
| | | | llvm-svn: 41808
* Add missing index versions of instructions to the map.Bill Wendling2007-09-071-1/+7
| | | | llvm-svn: 41776
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-072-6/+8
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* LVXL and STVXL are also a load and store resp.Bill Wendling2007-09-051-0/+2
| | | | llvm-svn: 41733
* Add the 64-bit versions of the DS* Altivec instructions.Bill Wendling2007-09-051-14/+45
| | | | llvm-svn: 41717
* Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.Evan Cheng2007-09-041-0/+10
| | | | llvm-svn: 41711
* Enhance APFloat to retain bits of NaNs (fixes oggenc).Dale Johannesen2007-08-311-5/+5
| | | | | | | Use APFloat interfaces for more references, mostly of ConstantFPSDNode. llvm-svn: 41632
* Add a variant of foldMemoryOperand to fold any load / store, not just load / ↵Evan Cheng2007-08-301-0/+5
| | | | | | store from / to stack slots. llvm-svn: 41597
* Use i64 on a PPC64 machineBill Wendling2007-08-301-1/+1
| | | | llvm-svn: 41590
* rename isOperandValidForConstraint to LowerAsmOperandForConstraint, Chris Lattner2007-08-252-14/+27
| | | | | | changing the interface to allow for future changes. llvm-svn: 41384
* Disable EH generation until PPC works 100%.Chris Lattner2007-08-241-1/+1
| | | | llvm-svn: 41360
* new exampleChris Lattner2007-08-231-0/+17
| | | | llvm-svn: 41318
* Fix arguments for some Altivec instructions. From SWB.Dale Johannesen2007-08-091-9/+15
| | | | llvm-svn: 40957
* Fix spelling of mtvscr and mfvscr.Dale Johannesen2007-08-071-2/+2
| | | | llvm-svn: 40908
* long double patch 2 of N. Handle it in TargetData.Dale Johannesen2007-08-031-2/+2
| | | | | | | (I've tried to get the info right for all targets, but I'm not expert on all of them - check yours.) llvm-svn: 40792
* More explicit keywords.Dan Gohman2007-08-021-1/+1
| | | | llvm-svn: 40757
* Some out operands were incorrectly specified as input operands.Evan Cheng2007-08-012-17/+17
| | | | llvm-svn: 40697
* Vector fneg must be expanded into fsub -0.0, X.Evan Cheng2007-07-303-2/+21
| | | | llvm-svn: 40586
* Support for trampolines, except for X86 codegen which isDuncan Sands2007-07-271-1/+4
| | | | | | still under discussion. llvm-svn: 40549
* Don't ignore the return value of AsmPrinter::doInitialization andDan Gohman2007-07-251-8/+6
| | | | | | AsmPrinter::doFinalization. llvm-svn: 40487
* Fix debug info and globals filled with zeros.Nick Lewycky2007-07-252-13/+26
| | | | llvm-svn: 40483
* No more noResults.Evan Cheng2007-07-213-14/+11
| | | | llvm-svn: 40132
* Added -print-emitted-asm to print out JIT generated asm to cerr.Evan Cheng2007-07-202-4/+8
| | | | llvm-svn: 40123
* Oops. These stores actually produce results.Evan Cheng2007-07-202-9/+9
| | | | llvm-svn: 40074
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-196-463/+479
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Long live the exception handling!Anton Korobeynikov2007-07-142-4/+6
| | | | | | | | | | | | | | | This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
* Skeleton of post-RA scheduler; doesn't do anything yet.Dale Johannesen2007-07-131-1/+1
| | | | | | | Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. llvm-svn: 39816
* Assert when TLS is not implemented.Lauro Ramos Venancio2007-07-111-0/+7
| | | | llvm-svn: 39737
* Change getCopyToParts and getCopyFromParts to always use target-endianDan Gohman2007-07-091-2/+2
| | | | | | | | register ordering, for both physical and virtual registers. Update the PPC target lowering for calls to expect registers for the call result to already be in target order. llvm-svn: 38471
* The various "getModuleMatchQuality" implementations should returnChris Lattner2007-07-091-0/+3
| | | | | | zero if they see a target triple they don't understand. llvm-svn: 38463
* Do away with ImmutablePredicateOperand.Evan Cheng2007-07-061-2/+2
| | | | llvm-svn: 37961
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