| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | More ppc32 byval handling (bug fixes). Things | Dale Johannesen | 2008-03-08 | 1 | -3/+23 |
| | | | | | | | are looking pretty good now. llvm-svn: 48043 | ||||
| * | Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵ | Evan Cheng | 2008-03-08 | 1 | -0/+1 |
| | | | | | | | and prefetchnta instructions. llvm-svn: 48042 | ||||
| * | Add support for calls with i128 return values on ppc64. | Dan Gohman | 2008-03-08 | 1 | -3/+13 |
| | | | | | llvm-svn: 48041 | ||||
| * | PPC64 passes arguments of integral type in i64 registers, not i32. Reflect this | Bill Wendling | 2008-03-07 | 1 | -26/+43 |
| | | | | | | | | by promoting smaller integral values (i32 at this point) to i64, then truncating to get the wanted size. llvm-svn: 48030 | ||||
| * | Add support for lowering 128-bit shifts on ppc64. | Dan Gohman | 2008-03-07 | 1 | -44/+60 |
| | | | | | llvm-svn: 48029 | ||||
| * | Next bits of PPC byval handling. Basically functional | Dale Johannesen | 2008-03-07 | 1 | -7/+73 |
| | | | | | | | but there are bugs. llvm-svn: 48028 | ||||
| * | Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl). | Chris Lattner | 2008-03-07 | 2 | -6/+16 |
| | | | | | llvm-svn: 48027 | ||||
| * | Replace SDT_PPCShiftOp in favor of SDTIntBinOps. This allows it to work | Chris Lattner | 2008-03-07 | 1 | -6/+3 |
| | | | | | | | with 32 or 64-bit operands/results. llvm-svn: 48026 | ||||
| * | Next bit of PPC ByVal handling; call-site code seems | Dale Johannesen | 2008-03-05 | 1 | -3/+11 |
| | | | | | | | correct now. llvm-svn: 47978 | ||||
| * | Removed spurious EnablePPCRS check. | Bill Wendling | 2008-03-04 | 1 | -4/+3 |
| | | | | | llvm-svn: 47918 | ||||
| * | Move PPC lowering functions into PPCTargetLowering | Dale Johannesen | 2008-03-04 | 2 | -28/+120 |
| | | | | | | | | class (cosmetic). First piece of byval implementation; this doesn't work yet. No functional change. llvm-svn: 47917 | ||||
| * | Use a command-line option to turn register scavenging on/off for PPC. | Bill Wendling | 2008-03-04 | 2 | -39/+51 |
| | | | | | llvm-svn: 47915 | ||||
| * | This is the initial check-in for adding register scavenging to PPC. (Currently, | Bill Wendling | 2008-03-03 | 5 | -104/+365 |
| | | | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863 | ||||
| * | add a note | Chris Lattner | 2008-03-02 | 1 | -0/+39 |
| | | | | | llvm-svn: 47830 | ||||
| * | Evan implemented this. | Chris Lattner | 2008-03-02 | 1 | -23/+0 |
| | | | | | llvm-svn: 47827 | ||||
| * | Use enumeration for preffered EH dwarf encoding reason | Anton Korobeynikov | 2008-02-29 | 2 | -6/+8 |
| | | | | | llvm-svn: 47770 | ||||
| * | Interface of getByValTypeAlignment differed between | Dale Johannesen | 2008-02-28 | 2 | -0/+16 |
| | | | | | | | | | generic & x86 versions; change generic to follow x86 and improve comments. Add PPC version (not right for non-Darwin.) llvm-svn: 47734 | ||||
| * | Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to ↵ | Evan Cheng | 2008-02-28 | 1 | -2/+2 |
| | | | | | | | 16-byte boundaries. llvm-svn: 47703 | ||||
| * | EHPreferredDataFormat hook for PPC targets. Looks like Darwin | Anton Korobeynikov | 2008-02-27 | 2 | -1/+30 |
| | | | | | | | uses the same encoding everywhere. Linux FIXME'ed. llvm-svn: 47701 | ||||
| * | Don't hard-code the mask size to be 32, which is incorrect on ppc64 | Dan Gohman | 2008-02-27 | 1 | -3/+5 |
| | | | | | | | | and was causing aborts with the new APInt changes. This may also be fixing an obscure ppc64 bug. llvm-svn: 47692 | ||||
| * | Final de-tabification. | Bill Wendling | 2008-02-27 | 1 | -3/+3 |
| | | | | | llvm-svn: 47663 | ||||
| * | Convert the last remaining users of the non-APInt form of | Dan Gohman | 2008-02-27 | 2 | -16/+24 |
| | | | | | | | | ComputeMaskedBits to use the APInt form, and remove the non-APInt form. llvm-svn: 47654 | ||||
| * | Rename PrintableName to Name. | Bill Wendling | 2008-02-26 | 1 | -1/+1 |
| | | | | | llvm-svn: 47629 | ||||
| * | Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool | Bill Wendling | 2008-02-26 | 2 | -2/+2 |
| | | | | | | | would have been a Godsend here! llvm-svn: 47625 | ||||
| * | Some platforms use the same name for 32-bit and 64-bit registers (like | Bill Wendling | 2008-02-24 | 1 | -34/+35 |
| | | | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. llvm-svn: 47534 | ||||
| * | Remove bunch of gcc 4.3-related warnings from Target | Anton Korobeynikov | 2008-02-20 | 2 | -3/+4 |
| | | | | | llvm-svn: 47369 | ||||
| * | I cannot find a libgcc function for this builtin. Therefor expanding it to ↵ | Andrew Lenharth | 2008-02-16 | 1 | -1/+2 |
| | | | | | | | a noop (which is how it use to be treated). If someone who knows the x86 backend better than me could tell me how to get a lock prefix on an instruction, that would be nice to complete x86 support. llvm-svn: 47213 | ||||
| * | Handle \n's in value names for more targets. The asm printers | Chris Lattner | 2008-02-15 | 1 | -6/+21 |
| | | | | | | | really really really need refactoring :( llvm-svn: 47171 | ||||
| * | Cosmetics. | Dale Johannesen | 2008-02-15 | 1 | -6/+3 |
| | | | | | llvm-svn: 47168 | ||||
| * | Remove warning about 64-bit code on processor | Dale Johannesen | 2008-02-15 | 1 | -4/+0 |
| | | | | | | | that doesn't support it. Per Chris. llvm-svn: 47162 | ||||
| * | Rewrite tblgen handling of subtarget features so | Dale Johannesen | 2008-02-14 | 3 | -0/+3 |
| | | | | | | | | | | | it follows the order of the enum, not alphabetical. The motivation is to make -mattr=+ssse3,+sse41 select SSE41 as it ought to. Added "ignored" enum values of 0 to PPC and SPU to avoid compiler warnings. llvm-svn: 47143 | ||||
| * | Change how FP immediates are handled. | Nate Begeman | 2008-02-14 | 1 | -3/+0 |
| | | | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. llvm-svn: 47121 | ||||
| * | Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits | Dan Gohman | 2008-02-13 | 2 | -2/+2 |
| | | | | | | | to pass the mask APInt by value, not by reference. llvm-svn: 47096 | ||||
| * | Enable exception handling int JIT | Nicolas Geoffray | 2008-02-13 | 1 | -0/+11 |
| | | | | | llvm-svn: 47079 | ||||
| * | Fix the PPC JIT regressions by encoding zeroreg as 0 for BLR. | Chris Lattner | 2008-02-13 | 1 | -0/+1 |
| | | | | | llvm-svn: 47067 | ||||
| * | don't try to avoid inserting loads when lowering FORMAL_ARGUMENTS. | Chris Lattner | 2008-02-13 | 1 | -12/+5 |
| | | | | | | | DAGCombine is now quite good at zapifying them. llvm-svn: 47053 | ||||
| * | readme updates | Nate Begeman | 2008-02-13 | 1 | -0/+9 |
| | | | | | llvm-svn: 47051 | ||||
| * | Make register scavenging happy by not using a reg (CR0) that isn't defined | Nate Begeman | 2008-02-13 | 1 | -1/+1 |
| | | | | | llvm-svn: 47045 | ||||
| * | commuteInstr() can now commute non-ssa machine instrs. | Evan Cheng | 2008-02-13 | 1 | -0/+10 |
| | | | | | llvm-svn: 47043 | ||||
| * | Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t. | Dan Gohman | 2008-02-13 | 2 | -8/+7 |
| | | | | | | | | Add an overload that supports the uint64_t interface for use by clients that haven't been updated yet. llvm-svn: 47039 | ||||
| * | Revert r46916 PPCTargetAsmInfo.cpp. | Evan Cheng | 2008-02-12 | 1 | -2/+2 |
| | | | | | llvm-svn: 47020 | ||||
| * | additional missing feature | Nate Begeman | 2008-02-11 | 1 | -0/+1 |
| | | | | | llvm-svn: 46948 | ||||
| * | Rename MRegisterInfo to TargetRegisterInfo. | Dan Gohman | 2008-02-10 | 6 | -7/+9 |
| | | | | | llvm-svn: 46930 | ||||
| * | Match GCC's behaviour for these sections. | Nick Lewycky | 2008-02-10 | 1 | -2/+2 |
| | | | | | llvm-svn: 46916 | ||||
| * | It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵ | Evan Cheng | 2008-02-08 | 2 | -4/+7 |
| | | | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893 | ||||
| * | Follow Chris' suggestion; change the PseudoSourceValue accessors | Dan Gohman | 2008-02-07 | 1 | -1/+1 |
| | | | | | | | | to return pointers instead of references, since this is always what is needed. llvm-svn: 46857 | ||||
| * | Re-apply the memory operand changes, with a fix for the static | Dan Gohman | 2008-02-06 | 1 | -21/+27 |
| | | | | | | | | | initializer problem, a minor tweak to the way the DAGISelEmitter finds load/store nodes, and a renaming of the new PseudoSourceValue objects. llvm-svn: 46827 | ||||
| * | Ident mnemonics appropriately | Nate Begeman | 2008-02-05 | 1 | -4/+4 |
| | | | | | llvm-svn: 46746 | ||||
| * | Dwarf requires variable entries to be in the source order. Right now, since ↵ | Evan Cheng | 2008-02-04 | 1 | -1/+0 |
| | | | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724 | ||||
| * | Get rid of the annoying blank lines before labels. | Evan Cheng | 2008-02-02 | 1 | -2/+0 |
| | | | | | llvm-svn: 46667 | ||||

