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* PPC: Optimize rldicl generation for masked shiftsHal Finkel2013-11-201-1/+15
| | | | | | | | | | | | | | Masking operations (where only some number of the low bits are being kept) are selected to rldicl(x, 0, mb). If x is a logical right shift (which would become rldicl(y, 64-n, n)), we might be able to fold the two instructions together: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb) for n <= mb The right shift is really a left rotate followed by a mask, and if the explicit mask is a more-restrictive sub-mask of the mask implied by the shift, only one rldicl is needed. llvm-svn: 195185
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-194-1/+9
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-184-9/+1
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-154-1/+9
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Avoid illegal integer promotion in fastiselBob Wilson2013-11-151-7/+2
| | | | | | | | | | | | | | | | | Stop folding constant adds into GEP when the type size doesn't match. Otherwise, the adds' operands are effectively being promoted, changing the conditions of an overflow. Results are different when: sext(a) + sext(b) != sext(a + b) Problem originally found on x86-64, but also fixed issues with ARM and PPC, which used similar code. <rdar://problem/15292280> Patch by Duncan Exon Smith! llvm-svn: 194840
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+10
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. llvm-svn: 194384
* Use StringRef::startswith_lower. No functionality change.Rui Ueyama2013-10-311-4/+4
| | | | llvm-svn: 193796
* Add a helper getSymbol to AsmPrinter.Rafael Espindola2013-10-292-21/+21
| | | | llvm-svn: 193627
* Add support for the VSX target attribute. No functional changeEric Christopher2013-10-162-0/+3
| | | | | | as we don't actually use it to emit any code yet. llvm-svn: 192837
* Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-3/+3
| | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. llvm-svn: 192760
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-083-2/+72
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-12/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.Bill Schmidt2013-09-261-1/+3
| | | | | | | | When generating code for shared libraries, even local calls may be intercepted, so we need a nop after the call for the linker to fix up the TOC. Test case adapted from the one provided in PR17354. llvm-svn: 191440
* PPC: Allow partial fills in writeNopData()David Majnemer2013-09-261-4/+7
| | | | | | | | | | | | | | | | | | When asked to pad an irregular number of bytes, we should fill with zeros. This is consistent with the behavior specified in the AIX Assembler Language Reference as well as other LLVM and binutils assemblers. N.B. There is a small deviation from binutils' PPC assembler: when handling pads which are greater than 4 bytes but not mod 4, binutils will not emit any NOP sequences at all and only use zeros. This may or may not be a bug but there is no excellent rationale as to why that behavior is important to emulate. If that behavior is needed, we can change writeNopData() to behave in the same way. This fixes PR17352. llvm-svn: 191426
* PPC: Do not introduce ISD nodes for fctid and fctiwDavid Majnemer2013-09-263-8/+6
| | | | llvm-svn: 191421
* PPC: Add support for fctid and fctiwDavid Majnemer2013-09-263-4/+12
| | | | | | | | | Encodings were checked against the Power ISA documents and double checked against binutils. This fixes PR17350. llvm-svn: 191419
* MC: Add support for treating $ as a reference to the PCDavid Majnemer2013-09-251-0/+2
| | | | | | | | | | | | | | | | | The binutils assembler supports a mode called DOLLAR_DOT which treats the dollar sign token as a reference to the current program counter if the dollar sign doesn't precede a constant or identifier. This commit adds a new MCAsmInfo flag stating whether or not a given target supports this interpretation of the dollar sign token; by default, this flag is not enabled. Further, enable this flag for PPC. The system assembler for AIX and binutils both support using the dollar sign in this manner. This fixes PR17353. llvm-svn: 191368
* MC: Remove vestigial PCSymbol field from AsmInfoDavid Majnemer2013-09-251-3/+0
| | | | llvm-svn: 191362
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-1/+3
| | | | | | | | | | | | | | | | | Previously, the DAGISel function WalkChainUsers was spotting that it had entered already-selected territory by whether a node was a MachineNode (amongst other things). Since it's fairly common practice to insert MachineNodes during ISelLowering, this was not the correct check. Looking around, it seems that other nodes get their NodeId set to -1 upon selection, so this makes sure the same thing happens to all MachineNodes and uses that characteristic to determine whether we should stop looking for a loop during selection. This should fix PR15840. llvm-svn: 191165
* Correct the pre-increment load latencies in the PPC A2 itineraryHal Finkel2013-09-221-3/+3
| | | | | | | | Pre-increment loads are microcoded on the A2, and the address increment occurs only after the load completes. As a result, the latency of the GPR address update is an additional 2 cycles on top of the load latency. llvm-svn: 191156
* [PowerPC] Add a FIXME.Bill Schmidt2013-09-171-0/+4
| | | | | | | | Documenting a design choice to generate only medium model sequences for TLS addresses at this time. Small and large code models could be supported if necessary. llvm-svn: 190883
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-172-8/+22
| | | | | | | | | | | | | | Large code model on PPC64 requires creating and referencing TOC entries when using the addis/ld form of addressing. This was not being done in all cases. The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two test cases are also modified to reflect this requirement. Fast-isel was not creating correct code for loading floating-point constants using large code model. This also requires the addis/ld form of addressing. Previously we were using the addis/lfd shortcut which is only applicable to medium code model. One test case is modified to reflect this requirement. llvm-svn: 190882
* [PowerPC] Fix PR17155 - Ignore COPY_TO_REGCLASS during emit.Bill Schmidt2013-09-161-1/+8
| | | | | | | | | Fast-isel generates a COPY_TO_REGCLASS for widening f32 to f64, which is a nop on PPC64. This is needed to keep the register class system happy, but on the fast-isel path it is not removed before emit as it is for DAG select. Ignore this op when emitting instructions. llvm-svn: 190795
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-1/+2
| | | | | | | | | | | | | | | | | | | This is a re-commit of r190764, with an extra check to make sure that we're not performing the transformation on illegal types (a small test case has been added for this as well). Original commit message: The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190771
* Revert r190764: PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-0/+1
| | | | | | | | | | | | | | | | | This is causing test-suite failures. Original commit message: The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190765
* PPC: Don't restrict lvsl generation to after type legalizationHal Finkel2013-09-151-1/+0
| | | | | | | | | | | | | The PPC backend uses a target-specific DAG combine to turn unaligned Altivec loads into a permutation-based sequence when possible. Unfortunately, the target-specific DAG combine is not always called on all loads of interest (sometimes the routines in DAGCombine call CombineTo such that the new node and users are not added to the worklist); allowing the combine to trigger early (before type legalization) mitigates this problem. Because the autovectorizers only create legal vector types, I don't expect a lot of cases where this optimization is enabled by type legalization in practice. llvm-svn: 190764
* Add missing break statement in PPCISelLoweringHal Finkel2013-09-131-0/+2
| | | | | | As it turns out, not a problem in practice, but it should be there. llvm-svn: 190720
* Remove an unused variable, fixing -Werror build with latest Clang.Chandler Carruth2013-09-121-1/+0
| | | | llvm-svn: 190640
* Fix PPC ABI for ByVal structs with vector membersHal Finkel2013-09-121-9/+49
| | | | | | | | | | When a structure is passed by value, and that structure contains a vector member, according to the PPC ABI, the structure will receive enhanced alignment (so that the vector within the structure will always be aligned). This should resolve PR16641. llvm-svn: 190636
* Make the PPC fast-math sqrt expansion safe at 0Hal Finkel2013-09-121-1/+21
| | | | | | | | | | | In fast-math mode sqrt(x) is calculated using the fast expansion of the reciprocal of the reciprocal sqrt expansion. The reciprocal and reciprocal sqrt expansions use the associated estimate instructions along with some Newton iterations. Unfortunately, as a result, sqrt(0) was being calculated as NaN, which is not correct. Now we explicitly return a result of zero if the input is zero. llvm-svn: 190624
* Implement asm support for a few PowerPC bookIII that are needed for assemblingRoman Divacky2013-09-124-0/+112
| | | | | | FreeBSD kernel. llvm-svn: 190618
* Mark PPC MFTB and DST (and friends) as deprecatedHal Finkel2013-09-126-25/+56
| | | | | | | | Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. llvm-svn: 190605
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* PPC: Enable aggressive anti-dependency breakingHal Finkel2013-09-123-11/+3
| | | | | | | | | | | | | | | | | | | | Aggressive anti-dependency breaking is enabled by default for all PPC cores. This provides a general speedup on the P7 and other platforms (among other factors, the instruction group formation for the non-embedded PPC cores is done during post-RA scheduling). In order to do this safely, the incompatibility between uses of the MFOCRF instruction and anti-dependency breaking are resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed FIXME, the problem was that MFOCRF's output is sensitive to the identify of the source register, and always paired with a shift to undo this effect. Because anti-dependency breaking is unaware of this hidden dependency of the shift amount on the source register of the MFOCRF instruction, changing that register must be inhibited. Two test cases were adjusted: The SjLj test was made more insensitive to register choices and scheduling; the saveCR test disabled anti-dependency breaking because part of what it is testing is proper register reuse. llvm-svn: 190587
* Greatly simplify the PPC A2 scheduling itineraryHal Finkel2013-09-113-726/+118
| | | | | | | | | | | As Andy pointed out to me a long time ago, there are no structural hazards in the later pipeline stages of the A2, and so modeling them is useless. Also, modeling the top pre-dispatch stages is deceiving because, when multiple hardware threads are active, those resources are shared among the threads. The bypass definitions were mostly wrong, and so those have been removed. The resulting itinerary is much simpler, and more accurate. llvm-svn: 190562
* Enable MI scheduling (and CodeGen AA) by default for embedded PPC coresHal Finkel2013-09-113-2/+52
| | | | | | | For embedded PPC cores (especially the A2 core), using the MI scheduler with AA is far superior to the other scheduling options. llvm-svn: 190558
* Implement TTI getUnrollingPreferences for PowerPCHal Finkel2013-09-111-0/+9
| | | | | | | | The PowerPC A2 core greatly benefits from aggressive concatenation unrolling; use the new getUnrollingPreferences to enable this by default when targeting the PPC A2 core. llvm-svn: 190549
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-5/+5
| | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> llvm-svn: 190290
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-012-43/+47
| | | | llvm-svn: 189728
* [PowerPC] Fast-isel cleanup patch.Bill Schmidt2013-08-311-20/+37
| | | | | | | | | | | | | | | | | | | | Here are a few miscellaneous things to tidy up the PPC64 fast-isel implementation. I corrected a couple of commentary lapses, and added documentation of future opportunities. I also implemented TargetMaterializeAlloca, which I somehow forgot when I split up the original huge patch. Finally, I decided to delete SelectCmp. I hadn't previously hooked it in to TargetSelectInstruction(), and when I did I realized it wasn't serving any useful purpose. This is only useful for compares that don't feed a branch in the same block, and to handle that we would have to have logic to interpret i1 as a condition register. This could probably be done, but would require Unseemly Hackery, and honestly does not seem worth the hassle. This ends the current patch series. llvm-svn: 189715
* [PowerPC] Add integer truncation support to fast-isel.Bill Schmidt2013-08-301-0/+31
| | | | | | | | | | | | This is the last substantive patch I'm planning for fast-isel in the near future, adding fast selection of integer truncates. There are certainly more things that can be improved (many of which are called out in FIXMEs), but for now we are catching most of the important cases. I'll document some of the remaining work in a cleanup patch shortly. llvm-svn: 189706
* Correct partially defined variableBill Schmidt2013-08-301-1/+2
| | | | llvm-svn: 189705
* [PowerPC] Call support for fast-isel.Bill Schmidt2013-08-303-3/+338
| | | | | | | | | This patch adds fast-isel support for calls (but not intrinsic calls or varargs calls). It also removes a badly-formed assert. There are some new tests just for calls, and also for folding loads into arguments on calls to avoid extra extends. llvm-svn: 189701
* [PowerPC] Add handling for conversions to fast-isel.Bill Schmidt2013-08-304-0/+288
| | | | | | | | | Yet another chunk of fast-isel code. This one handles various conversions involving floating-point. (It also includes some miscellaneous handling throughout the back end for LWA_32 and LWAX_32 that should have been part of the load-store patch.) llvm-svn: 189677
* [PowerPC] Handle selection of compare instructions in fast-isel.Bill Schmidt2013-08-301-0/+18
| | | | | | | Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
* Remove bogus debug statement. Sheesh.Bill Schmidt2013-08-301-4/+2
| | | | llvm-svn: 189638
* [PowerPC] Add loads, stores, and related things to fast-isel.Bill Schmidt2013-08-303-7/+776
| | | | | | | | | | | | | | | | | | | | | | | | | This is the next big chunk of fast-isel code. The primary purpose is to implement selection of loads and stores, but there is a lot of drag-along to support this. The common code to analyze addresses for both loads and stores is substantial. It's also necessary to add the materialization code for global values. Related to load-store processing is the code to fold loads into integer extends, since otherwise we generate lots of redundant instructions. We also need to add some overrides to some FastEmit routines to ensure we don't assign GPR 0 to a virtual register when this would change the meaning of an instruction. I added handling selection of a few binary arithmetic instructions, to enable committing some test cases I wrote a while back. Finally, ap couple of miscellaneous changes: * I cleaned up some poor style from a previous patch in PPCISelLowering.cpp, pointed out by David Blaikie. * I enlarged the Addr.Offset field to avoid sign problems with 32-bit offsets. llvm-svn: 189636
* Fix use of uninitialized value added in r189400 (found by MemorySanitizer)Alexey Samsonov2013-08-281-4/+3
| | | | llvm-svn: 189456
* Given target assembler parsers a chance to handle variant expressionsJoerg Sonnenberger2013-08-272-3/+31
| | | | | | | first. Use this to turn the PPC modifiers into PPC specific expressions, allowing them to work on constants. llvm-svn: 189400
* Revert "Fix the build broken by r189315." and "Move everything depending on ↵Charles Davis2013-08-272-50/+46
| | | | | | | | | Object/MachOFormat.h over to Support/MachO.h." This reverts commits r189319 and r189315. r189315 broke some tests on what I believe are big-endian platforms. llvm-svn: 189321
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