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* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-3/+3
| | | | llvm-svn: 116018
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-284-4/+4
| | | | llvm-svn: 115005
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | llvm-svn: 114999
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-8/+5
| | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. llvm-svn: 114471
* update a bunch of code to use the MachinePointerInfo version of getStore.Chris Lattner2010-09-211-26/+30
| | | | llvm-svn: 114461
* eliminate an old SelectionDAG::getTruncStore method, propagatingChris Lattner2010-09-211-4/+6
| | | | | | MachinePointerInfo around more. llvm-svn: 114452
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-211-1/+2
| | | | | | SelectionDAG::getExtLoad overload, and eliminate it. llvm-svn: 114446
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-211-25/+30
| | | | llvm-svn: 114410
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-211-1/+2
| | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. llvm-svn: 114401
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-212-6/+9
| | | | llvm-svn: 114391
* add a readme.Chris Lattner2010-09-191-0/+25
| | | | llvm-svn: 114303
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-2/+2
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* zap dead code.Chris Lattner2010-09-043-11/+0
| | | | llvm-svn: 113073
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-11/+8
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 llvm-svn: 112241
* tyopsGabor Greif2010-08-231-1/+1
| | | | llvm-svn: 111835
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-171-1/+1
| | | | llvm-svn: 111241
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-062-2/+2
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-062-2/+2
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-052-2/+2
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Implement target specific getDebugValueLocation().Devang Patel2010-08-041-0/+14
| | | | llvm-svn: 110256
* Use indirect calls in PowerPC JIT.Torok Edwin2010-08-043-10/+31
| | | | | | | | | See PR5201. There is no way to know if direct calls will be within the allowed range for BL. Hence emit all calls as indirect when in JIT mode. Without this long-running applications will fail to JIT on PowerPC with a relocation failure. llvm-svn: 110246
* PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.Eli Friedman2010-08-021-3/+3
| | | | llvm-svn: 109998
* PPC doesn't supported VLA with large alignment. This wasDale Johannesen2010-07-301-2/+2
| | | | | | | | formerly rejected by the FE, so asserted in the BE; now the FE only warns, so we treat it as a legitimate fatal error in PPC BE. This means the test for the feature won't pass, so it's xfail'd. llvm-svn: 109892
* fix constness warningsGabor Greif2010-07-231-1/+2
| | | | llvm-svn: 109224
* eliminate the TargetInstrInfo::GetInstSizeInBytes hook. Chris Lattner2010-07-221-1/+1
| | | | | | | | ARM/PPC/MSP430-specific code (which are the only targets that implement the hook) can directly reference their target-specific instrinfo classes. llvm-svn: 109171
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-67/+0
| | | | llvm-svn: 108567
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-163-4/+4
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Emit COPY instead of FMR/FMSD instructions for floating point conversion onJakob Stoklund Olesen2010-07-162-12/+9
| | | | | | PowerPC. llvm-svn: 108555
* Teach PPCInstrInfo::storeRegToStackSlot and loadRegFromStackSlot to add memoryJakob Stoklund Olesen2010-07-161-0/+19
| | | | | | | | | operands. Hopefully this fixes the llvm-gcc-powerpc-darwin9 buildbot. It really shouldn't since missing memoperands should not affect correctness. llvm-svn: 108540
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-132/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for PowerPC.Jakob Stoklund Olesen2010-07-112-36/+30
| | | | llvm-svn: 108083
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-071-1/+1
| | | | | | for consistency sake. llvm-svn: 107820
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-11/+20
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Propagate debug loc.Devang Patel2010-07-061-4/+5
| | | | llvm-svn: 107710
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-17/+29
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Revert r107655.Dan Gohman2010-07-061-29/+17
| | | | llvm-svn: 107668
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-17/+29
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-032-19/+13
| | | | | | slots so it's always false. llvm-svn: 107550
* Remove initialized but otherwise unused variables.Duncan Sands2010-06-291-1/+0
| | | | llvm-svn: 107127
* The hasMemory argument is irrelevant to how the argumentDale Johannesen2010-06-252-9/+3
| | | | | | | | | for an "i" constraint should get lowered; PR 6309. While this argument was passed around a lot, this is the only place it was used, so it goes away from a lot of other places. llvm-svn: 106893
* Eliminate unnecessary uses of getZExtValue().Dan Gohman2010-06-181-3/+3
| | | | llvm-svn: 106279
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-8/+8
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-1/+1
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-1/+1
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-1/+1
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-14/+12
| | | | llvm-svn: 105344
* cleanupRafael Espindola2010-06-022-137/+0
| | | | llvm-svn: 105322
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104704
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-11/+19
| | | | | | This reverts commit 104654. llvm-svn: 104660
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-19/+11
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. llvm-svn: 104654
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