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* Added source file/line correspondence for dwarf (PowerPC only at this point.)Jim Laskey2005-12-162-0/+17
| | | | llvm-svn: 24748
* Weak and linkonce global vars should still have a .globl emitted for themChris Lattner2005-12-161-1/+2
| | | | llvm-svn: 24747
* Add a second vector type to the VRRC register class, and fix some patternsNate Begeman2005-12-162-6/+6
| | | | | | so that tablegen can infer all types. llvm-svn: 24746
* Update the darwin handling of linkonce & weak functions and GV stubs. ThisChris Lattner2005-12-161-57/+63
| | | | | | should work in all permutations. llvm-svn: 24728
* Remove a now unused statistic.Nate Begeman2005-12-141-1/+0
| | | | llvm-svn: 24720
* Use the new predicate support that Evan Cheng added to remove some codeNate Begeman2005-12-142-57/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | from the DAGToDAG cpp file. This adds pattern support for vector and scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and does the right thing in the presence of -disable-excess-fp-precision. Allows us to match: void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 %tmp3 = add <4 x float> %tmp2, %tmp1 store <4 x float> %tmp3, <4 x float> *%a ret void } As: _foo: li r2, 0 lvx v0, r2, r3 vmaddfp v0, v0, v0, v0 stvx v0, r2, r3 blr Or, with llc -disable-excess-fp-precision, _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v1, v0, v0, v1 vaddfp v0, v1, v0 stvx v0, r2, r3 blr llvm-svn: 24719
* Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS.Evan Cheng2005-12-141-4/+11
| | | | llvm-svn: 24716
* Add support for fmul node of type v4f32.Nate Begeman2005-12-142-0/+21
| | | | | | | | | | | | | | | | | | | | | | void %foo(<4 x float> * %a) { entry: %tmp1 = load <4 x float> * %a; %tmp2 = mul <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float> *%a ret void } Is selected to: _foo: li r2, 0 lvx v0, r2, r3 vxor v1, v1, v1 vmaddfp v0, v0, v0, v1 stvx v0, r2, r3 blr llvm-svn: 24701
* Prepare support for AltiVec multiply, divide, and sqrt.Nate Begeman2005-12-132-2/+16
| | | | llvm-svn: 24700
* Use the shared asmprinter code for printing special llvm globalsChris Lattner2005-12-131-33/+5
| | | | llvm-svn: 24695
* reindent a loop, unswitch a loop. No functionality changesChris Lattner2005-12-131-105/+109
| | | | llvm-svn: 24692
* Remove type casts that are no longer neededChris Lattner2005-12-112-6/+7
| | | | llvm-svn: 24661
* Fix the JIT failures from last night.Chris Lattner2005-12-111-1/+2
| | | | llvm-svn: 24659
* Add support for TargetConstantPool nodes to the dag isel emitter, and useNate Begeman2005-12-103-29/+40
| | | | | | | them in the PPC backend, to simplify some logic out of Select and SelectAddr. llvm-svn: 24657
* Add support patterns to many load and store instructions which willNate Begeman2005-12-092-76/+133
| | | | | | hopefully use patterns in the near future. llvm-svn: 24651
* Teach the PPC backend about the ctor and dtor list when not using __main andChris Lattner2005-12-091-0/+34
| | | | | | linking the entire program into one bc file. llvm-svn: 24645
* Add another important case we missChris Lattner2005-12-081-0/+19
| | | | llvm-svn: 24639
* Silence another annoying GCC warningChris Lattner2005-12-061-1/+1
| | | | llvm-svn: 24627
* Use new PPC-specific nodes to represent shifts which require the 6-bitChris Lattner2005-12-063-15/+40
| | | | | | | | | amount handling that PPC provides. These are generated by the lowering code and prevents the dag combiner from assuming (rightfully) that the shifts don't only look at 5 bits. This fixes a miscompilation of crafty with the new front-end. llvm-svn: 24615
* Add some explicit type casts so that tblgen knows the type of the shiftChris Lattner2005-12-051-5/+5
| | | | | | amount, which is not necessarily the same as the type being shifted. llvm-svn: 24594
* The basic fneg cases are already autogen'dChris Lattner2005-12-041-4/+2
| | | | llvm-svn: 24592
* Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgenChris Lattner2005-12-042-11/+12
| | | | | | improvements. llvm-svn: 24591
* Finish moving uncond br over to .td file, remove from .cpp file.Chris Lattner2005-12-042-4/+2
| | | | llvm-svn: 24590
* Define BR in the .td file now that Evan made tblgen smarter.Chris Lattner2005-12-042-5/+10
| | | | llvm-svn: 24589
* Make sure these get added into the codegenmap when appropriateChris Lattner2005-12-011-4/+5
| | | | llvm-svn: 24566
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-7/+8
| | | | | | work. This change has no effect on generated code. llvm-svn: 24563
* Cosmetic change, better reflects actual valuesNate Begeman2005-12-011-6/+5
| | | | llvm-svn: 24562
* Fix a regression caused by a patch earlier todayChris Lattner2005-12-011-1/+2
| | | | llvm-svn: 24561
* Use a getCopyToReg() variant to generate a flaggy CopyToReg node.Evan Cheng2005-12-011-8/+2
| | | | llvm-svn: 24558
* SelectNodeTo now returns N. Use it instead of return N directly.Chris Lattner2005-11-301-108/+81
| | | | llvm-svn: 24549
* Fix Regression/CodeGen/PowerPC/2005-11-30-vastart-crash.llChris Lattner2005-11-301-2/+6
| | | | llvm-svn: 24547
* No longer track value types for asm printer operands, and remove them asNate Begeman2005-11-301-30/+17
| | | | | | | an argument to every operand printing function. Requires some slight tweaks to x86, the only user. llvm-svn: 24541
* First chunk of actually generating vector code for packed types. TheseNate Begeman2005-11-301-11/+51
| | | | | | | | | | | | | | | | | | | | | | | changes allow us to generate the following code: _foo: li r2, 0 lvx v0, r2, r3 vaddfp v0, v0, v0 stvx v0, r2, r3 blr for this llvm: void %foo(<4 x float>* %a) { entry: %tmp1 = load <4 x float>* %a %tmp2 = add <4 x float> %tmp1, %tmp1 store <4 x float> %tmp2, <4 x float>* %a ret void } llvm-svn: 24534
* Represent the encoding of the SPR instructions as they actually are, soNate Begeman2005-11-292-8/+18
| | | | | | | that we can use the correct SPR numbers in the InstrInfo.td file. This is necessary to support VRsave. llvm-svn: 24521
* Hook up one type, v4f32, to the VR RegisterClass for now.Nate Begeman2005-11-291-0/+6
| | | | llvm-svn: 24517
* Add the remainder of the AltiVec 4 x float instructions. FurtherNate Begeman2005-11-292-14/+61
| | | | | | | enhancements will be necessary to teach the code generator that since there is no fmul, it will have to do vmaddfp, adding +0.0. llvm-svn: 24516
* No targets support line number info yet.Chris Lattner2005-11-291-0/+3
| | | | llvm-svn: 24513
* Add the majority of the vector machien value types we expect to support,Nate Begeman2005-11-291-1/+1
| | | | | | | and make a few changes to the legalization machinery to support more than 16 types. llvm-svn: 24511
* Fixed a comment bug:Evan Cheng2005-11-291-1/+1
| | | | | | createPPCPatternInstructionSelector -> createPPCISelPattern llvm-svn: 24510
* don't say this is i128, because it isn't yet. Hopefully nate will changeChris Lattner2005-11-291-1/+1
| | | | | | | this to be something sane, but in the mean time it is unused, so safe to make something bogus. llvm-svn: 24504
* Small tweaks noticed while on the plane.Nate Begeman2005-11-263-5/+10
| | | | llvm-svn: 24492
* Some first bits of AltiVec stuff: Instruction Formats, Encodings, andNate Begeman2005-11-233-1/+123
| | | | | | | | | | Registers. Apologies to Jim if the scheduling info so far isn't accurate. There's a few more things like VRsave support that need to be finished up in my local tree before I can commit code that Does The Right Thing for turning 4 x float into the various altivec packed float instructions. llvm-svn: 24489
* Use generic constant pool emission code in the AsmPrinter class.Chris Lattner2005-11-211-30/+4
| | | | llvm-svn: 24465
* Use the FunctionNumber provided by the AsmPrinter classChris Lattner2005-11-211-19/+15
| | | | llvm-svn: 24462
* Use CommentString where possible, fix a bug where aix mode wouldn't assembleChris Lattner2005-11-211-4/+4
| | | | | | due to basic blocks being misnamed. llvm-svn: 24459
* unify the darwin and aix constant pool printersChris Lattner2005-11-211-48/+28
| | | | llvm-svn: 24458
* Adjust to capitalized AsmPrinter method namesChris Lattner2005-11-211-11/+11
| | | | llvm-svn: 24456
* use PrivateGlobalPrefix for basic blocksChris Lattner2005-11-211-5/+6
| | | | llvm-svn: 24453
* This is now implemented in common codegen codeChris Lattner2005-11-211-20/+0
| | | | llvm-svn: 24446
* set PrivateGlobalPrefix on darwin, use it when printing out CP referencesChris Lattner2005-11-211-7/+9
| | | | llvm-svn: 24441
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