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* Rename and adjust processFixupValue.Rafael Espindola2017-06-301-5/+6
| | | | | | | It was not processing any value. All that it ever did was force relocations, so name it shouldForceRelocation. llvm-svn: 306906
* Make 0 argument getSubtargetImpl functions for the X86, AArch64, and PPC ↵Eric Christopher2017-06-301-0/+1
| | | | | | targets deleted so that no one is tempted to use them. llvm-svn: 306864
* To help readability of mightUseCTR pull out the inline asm handling support ↵Eric Christopher2017-06-291-10/+17
| | | | | | into a function. llvm-svn: 306762
* Make the PPCCTRLoops pass depend on being able to access the TargetMachine ↵Eric Christopher2017-06-293-49/+36
| | | | | | and clean up accordingly. llvm-svn: 306761
* [PowerPC] fix potential verification error on __tls_get_addrHiroshi Inoue2017-06-293-4/+22
| | | | | | | | | | This patch fixes a verification error with -verify-machineinstrs while expanding __tls_get_addr by not creating ADJCALLSTACKUP and ADJCALLSTACKDOWN if there is another ADJCALLSTACKUP in this basic block since nesting ADJCALLSTACKUP/ADJCALLSTACKDOWN is not allowed. Here, ADJCALLSTACKUP and ADJCALLSTACKDOWN are created as a fence for instruction scheduling to avoid _tls_get_addr is scheduled before mflr in the prologue (https://bugs.llvm.org//show_bug.cgi?id=25839). So if another ADJCALLSTACKUP exists before _tls_get_addr, we do not need to create a new ADJCALLSTACKUP. Differential Revision: https://reviews.llvm.org/D34347 llvm-svn: 306678
* Reuse existing variable. NFC.Rafael Espindola2017-06-281-2/+2
| | | | llvm-svn: 306582
* Don't repeat name in comment and format. NFC.Rafael Espindola2017-06-281-19/+15
| | | | llvm-svn: 306568
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-282-3/+4
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34531 llvm-svn: 306554
* [PowerPC] set optimization level in SelectionDAGISelHiroshi Inoue2017-06-273-6/+8
| | | | | | | | | PowerPC backend does not pass the current optimization level to SelectionDAGISel and so SelectionDAGISel works with the default optimization level regardless of the current optimization level. This patch makes the PowerPC backend set the optimization level correctly. Differential Revision: https://reviews.llvm.org/D34615 llvm-svn: 306367
* Simplify the processFixupValue interface. NFC.Rafael Espindola2017-06-241-4/+2
| | | | llvm-svn: 306202
* Remove redundant argument.Rafael Espindola2017-06-241-1/+1
| | | | llvm-svn: 306189
* ARM: move some logic from processFixupValue to applyFixup.Rafael Espindola2017-06-231-1/+2
| | | | | | | | | | | | processFixupValue is called on every relaxation iteration. applyFixup is only called once at the very end. applyFixup is then the correct place to do last minute changes and value checks. While here, do proper range checks again for fixup_arm_thumb_bl. We used to do it, but dropped because of thumb2. We now do it again, but use the thumb2 range. llvm-svn: 306177
* [PowerPC] fix potential verification errorsHiroshi Inoue2017-06-222-5/+12
| | | | | | This patch fixes trivial mishandling of 32-bit/64-bit instructions that may cause verification errors with -verify-machineinstrs. llvm-svn: 305984
* Use a MutableArrayRef. NFC.Rafael Espindola2017-06-211-1/+1
| | | | llvm-svn: 305968
* [PowerPC] define target hook isReallyTriviallyReMaterializable()Lei Huang2017-06-213-2/+29
| | | | | | | | | | | Define target hook isReallyTriviallyReMaterializable() to explicitly specify PowerPC instructions that are trivially rematerializable. This will allow the MachineLICM pass to accurately identify PPC instructions that should always be hoisted. Differential Revision: https://reviews.llvm.org/D34255 llvm-svn: 305932
* [PowerPC] fix trivial typos in comment, NFCHiroshi Inoue2017-06-201-1/+1
| | | | llvm-svn: 305813
* Rework logic and comment out the default relocation models for PPC.Eric Christopher2017-06-171-10/+13
| | | | llvm-svn: 305630
* Turn a large if block into a smaller early return for clarity.Eric Christopher2017-06-171-11/+10
| | | | llvm-svn: 305629
* Remove the old and unused PPC32 and PPC64TargetMachine classes.Eric Christopher2017-06-172-47/+4
| | | | llvm-svn: 305628
* Remove unused forward declaration.Eric Christopher2017-06-171-1/+0
| | | | llvm-svn: 305627
* Tidy up some calls to getRegister for readability.Eric Christopher2017-06-171-5/+6
| | | | llvm-svn: 305626
* [PPC] Remove isBarrier from CFENCE8's definition.Tim Shen2017-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is my misunderstanding on isBarrier. It's not for memory barriers, but for other control flow purposes. lwsync doesn't have it either. This fixes a simple crash with -verify-machineinstrs like below: define void @Foo() { entry: %tmp = load atomic i64, i64* undef acquire, align 8 unreachable } I deliberately don't want to check in the test, since there is little chance to regress on such a mistake. Such a test adds noise to the code base. I plan to check in first, since it fixes a crash, and the fix is obvious. Reviewers: kbarton, echristo Subscribers: sanjoy, nemanjai, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D34314 llvm-svn: 305624
* [MachineLICM] Hoist TOC-based address instructionsLei Huang2017-06-152-0/+15
| | | | | | | | | | | | | | | | | | Add condition for MachineLICM to safely hoist instructions that utilize non constant registers that are reserved. On PPC, global variable access is done through the table of contents (TOC) which is always in register X2. The ABI reserves this register in any functions that have calls or access global variables. A call through a function pointer involves saving, changing and restoring this register around the call and thus MachineLICM does not consider it to be invariant. We can however guarantee the register is preserved across the call and thus is invariant. Differential Revision: https://reviews.llvm.org/D33562 llvm-svn: 305490
* [PowerPC] fix potential verification errors on CFENCE8Hiroshi Inoue2017-06-151-1/+1
| | | | | | | | This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs. Differential Revision: https://reviews.llvm.org/D34208 llvm-svn: 305479
* Test commit - NFC.Lei Huang2017-06-141-1/+1
| | | | | | Modified a comment to confirm commit access functionality. llvm-svn: 305402
* Revert r304907 as it is causing some failures that I cannot reproduce.Nemanja Ivanovic2017-06-141-26/+0
| | | | | | Reverting this until a test case can be provided to aid the investigation. llvm-svn: 305372
* Test commit - NFC.Kit Barton2017-06-131-1/+1
| | | | | | Modified a comment to confirm commit access functionality. llvm-svn: 305309
* PPCISelLowering.cpp: Fix warnings in r305214. [-Wdocumentation]NAKAMURA Takumi2017-06-131-3/+3
| | | | llvm-svn: 305277
* [PowerPC] Match vec_revb builtins to P9 instructions.Tony Jiang2017-06-124-7/+105
| | | | | | | | | | | | Power9 has instructions that will reverse the bytes within an element for all sizes (half-word, word, double-word and quad-word). These can be used for the vec_revb builtins in altivec.h. However, we implement these to match vector shuffle nodes as that will cover both the builtins and vector shuffles that occur in the SDAG through other means. Differential Revision: https://reviews.llvm.org/D33690 llvm-svn: 305214
* [Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.Tony Jiang2017-06-124-5/+51
| | | | | | | | | | | Note that if we need the result of both the divide and the modulo then we compute the modulo based on the result of the divide and not using the new hardware instruction. Commit on behalf of STEFAN PINTILIE. Differential Revision: https://reviews.llvm.org/D33940 llvm-svn: 305210
* [DAG] add helper to bind memop chains; NFCISanjay Patel2017-06-121-0/+1
| | | | | | | | | | This step is just intended to reduce code duplication rather than change any functionality. A follow-up would be to replace PPCTargetLowering::spliceIntoChain() usage with this new helper. Differential Revision: https://reviews.llvm.org/D33649 llvm-svn: 305192
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-122-2/+2
| | | | | | | | | | | | | | Summary: The method TargetTransformInfo::getRegisterBitWidth() is declared const, but the type erasing implementation classes (TargetTransformInfo::Concept & TargetTransformInfo::Model) that were introduced by Chandler in https://reviews.llvm.org/D7293 do not have the method declared const. This is an NFC to tidy up the const consistency between TTI and its implementation. Reviewers: chandlerc, rnk, reames Reviewed By: reames Subscribers: reames, jfb, arsenm, dschuff, nemanjai, nhaehnle, javed.absar, sbc100, jgravelle-google, llvm-commits Differential Revision: https://reviews.llvm.org/D33903 llvm-svn: 305189
* [PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64Guozhi Wei2017-06-081-12/+26
| | | | | | | | | | In PPCBoolRetToInt bool value is changed to i32 type. On ppc64 it may introduce an extra zero extension for the return value. This patch changes the integer type to i64 to avoid the zero extension on ppc64. This patch fixed PR32442. Differential Revision: https://reviews.llvm.org/D31407 llvm-svn: 305001
* [Power9] Exploit vector integer extend instructionsZaara Syeda2017-06-081-0/+51
| | | | | | | | | | | | | | This patch adds build vector patterns to exploit the vector integer extend instructions: vextsb2w - Vector Extend Sign Byte To Word vextsb2d - Vector Extend Sign Byte To Doubleword vextsh2w - Vector Extend Sign Halfword To Word vextsh2d - Vector Extend Sign Halfword To Doubleword vextsw2d - Vector Extend Sign Word To Doubleword Differential Revision: https://reviews.llvm.org/D33510 llvm-svn: 304992
* [PowerPC] Eliminate integer compare instructions - vol. 5Nemanja Ivanovic2017-06-071-0/+26
| | | | | | | | Adds handling for i64 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33720 llvm-svn: 304907
* [PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic2017-06-071-0/+35
| | | | | | | | Adds handling for i32 SETNE comparison (both sign and zero extended). Differential Revision: https://reviews.llvm.org/D33718 llvm-svn: 304901
* Move Object format code to lib/BinaryFormat.Zachary Turner2017-06-074-8/+8
| | | | | | | | | | | | This creates a new library called BinaryFormat that has all of the headers from llvm/Support containing structure and layout definitions for various types of binary formats like dwarf, coff, elf, etc as well as the code for identifying a file from its magic. Differential Revision: https://reviews.llvm.org/D33843 llvm-svn: 304864
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-0622-32/+32
| | | | | | | | | | | | | | | | | | | | | | | | | I did this a long time ago with a janky python script, but now clang-format has built-in support for this. I fed clang-format every line with a #include and let it re-sort things according to the precise LLVM rules for include ordering baked into clang-format these days. I've reverted a number of files where the results of sorting includes isn't healthy. Either places where we have legacy code relying on particular include ordering (where possible, I'll fix these separately) or where we have particular formatting around #include lines that I didn't want to disturb in this patch. This patch is *entirely* mechanical. If you get merge conflicts or anything, just ignore the changes in this patch and run clang-format over your #include lines in the files. Sorry for any noise here, but it is important to keep these things stable. I was seeing an increasing number of patches with irrelevant re-ordering of #include lines because clang-format was used. This patch at least isolates that churn, makes it easy to skip when resolving conflicts, and gets us to a clean baseline (again). llvm-svn: 304787
* TargetMachine: Indicate whether machine verifier passes.Matthias Braun2017-05-311-0/+4
| | | | | | | | | | | | | This adds a callback to the LLVMTargetMachine that lets target indicate that they do not pass the machine verifier checks in all cases yet. This is intended to be a temporary measure while the targets are fixed allowing us to enable the machine verifier by default with EXPENSIVE_CHECKS enabled! Differential Revision: https://reviews.llvm.org/D33696 llvm-svn: 304320
* [PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.Sean Fertile2017-05-311-3/+12
| | | | | | | | | | Fixes PPCTTIImpl::getCacheLineSize() returning the wrong cache line size for newer ppc processors. Commiting on behalf of Stefan Pintilie. Differential Revision: https://reviews.llvm.org/D33656 llvm-svn: 304317
* [PPC] Inline expansion of memcmpZaara Syeda2017-05-313-0/+10
| | | | | | | | | | | | | | | This patch does an inline expansion of memcmp. It changes the memcmp library call into an inline expansion when the size is known at compile time and is under a target specified threshold. This expansion is implemented in CodeGenPrepare and expands into straight line code. The target specifies a maximum load size and the expansion works by using this size to load the two sources, compare, and exit early if a difference is found. It also has a special case when the memcmp result is used in a compare to zero equality. Differential Revision: https://reviews.llvm.org/D28637 llvm-svn: 304313
* [PowerPC] Fix a performance bug for PPC::XXPERMDI.Tony Jiang2017-05-314-13/+110
| | | | | | | | | | There are some VectorShuffle Nodes in SDAG which can be selected to XXPERMDI Instruction, this patch recognizes them and does the selection to improve the PPC performance. Differential Revision: https://reviews.llvm.org/D33404 llvm-svn: 304298
* [PowerPC] Eliminate integer compare instructions - vol. 3Nemanja Ivanovic2017-05-311-9/+64
| | | | | | | | | This patch builds upon https://reviews.llvm.org/rL302810 to add handling for the 64-bit SETEQ patterns. Differential Revision: https://reviews.llvm.org/D33369 llvm-svn: 304286
* [PowerPC] Eliminate integer compare instructions - vol. 2Nemanja Ivanovic2017-05-314-12/+230
| | | | | | | | | | | | This patch builds upon https://reviews.llvm.org/rL302810 to add handling for bitwise logical operations in general purpose registers. The idea is to keep the values in GPRs as long as possible - only extracting them to a condition register bit when no further operations are to be done. Differential Revision: https://reviews.llvm.org/D31851 llvm-svn: 304282
* TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFCMatthias Braun2017-05-301-2/+2
| | | | | | | | | | | TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTargetMachine instead of just to a TargetMachine. While at it, also change the constructor to take a reference instead of a pointer as the TM must not be nullptr. llvm-svn: 304247
* [SelectionDAG] Set ISD::FPOWI to Expand by defaultCraig Topper2017-05-301-3/+0
| | | | | | | | | | | | | | | | | Summary: Currently FPOWI defaults to Legal and LegalizeDAG.cpp turns Legal into Expand for this opcode because Legal is a "lie". This patch changes the default for this opcode to Expand and removes the hack from LegalizeDAG.cpp. It also removes all the code in the targets that set this opcode to Expand themselves since they can just rely on the default. Reviewers: spatel, RKSimon, efriedma Reviewed By: RKSimon Subscribers: jfb, dschuff, sbc100, jgravelle-google, nemanjai, javed.absar, andrew.w.kaylor, llvm-commits Differential Revision: https://reviews.llvm.org/D33530 llvm-svn: 304215
* [PPC] Fix assertion failure during binary encoding with -mcpu=pwr9Hiroshi Inoue2017-05-292-4/+18
| | | | | | | | | | | | | Summary clang -c -mcpu=pwr9 test/CodeGen/PowerPC/build-vector-tests.ll causes an assertion failure during the binary encoding. The failure occurs when a D-form load instruction takes two register operands instead of a register + an immediate. This patch fixes the problem and also adds an assertion to catch this failure earlier before the binary encoding (i.e. during lit test). The fix is from Nemanja Ivanovic @nemanjai. Differential Revision: https://reviews.llvm.org/D33482 llvm-svn: 304133
* LivePhysRegs: Rework constructor + documentation; NFCMatthias Braun2017-05-261-1/+1
| | | | | | | - Take reference instead of pointer to a TRI that cannot be nullptr. - Improve documentation comments. llvm-svn: 304038
* [PPC] Add text for assert.Tim Shen2017-05-251-1/+1
| | | | llvm-svn: 303940
* [PPC] Fix atomics lowering in DAG lowering.Tim Shen2017-05-251-1/+3
| | | | | | | | | | | I forgot to forward the chain, causing some missing instruction dependencies. The test crashes the compiler without this patch. Inspired by the test case, D33519 also tries to remove the extra sync. Differential Revision: https://reviews.llvm.org/D33573 llvm-svn: 303931
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