summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
* MC: Overhaul handling of .lcommBenjamin Kramer2012-09-071-1/+0
| | | | | | | | | | | | | - Darwin lied about not supporting .lcomm and turned it into zerofill in the asm parser. Push the zerofill-conversion down into macho-specific code. - This makes the tri-state LCOMMType enum superfluous, there are no targets without .lcomm. - Do proper error reporting when trying to use .lcomm with alignment on a target that doesn't support it. - .comm and .lcomm alignment was parsed in bytes on COFF, should be power of 2. - Fixes PR13755 (.lcomm crashes on ELF). llvm-svn: 163395
* Move the PPC TOC defs into the PPC64 InstrInfo file.Hal Finkel2012-09-052-3/+3
| | | | | | | | Since TOC is just defined for PPC64, move its definition to PPC64 td file. Patch by Adhemerval Zanella. llvm-svn: 163234
* Remove always true checks. Noticed by Adhemerval Zanella.Roman Divacky2012-09-031-2/+2
| | | | llvm-svn: 163117
* PPCISelLowering.cpp: Fix r162725.NAKAMURA Takumi2012-08-301-1/+5
| | | | | | | | [Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good! Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good. llvm-svn: 162916
* PPCISelLowering.cpp: Whitespace.NAKAMURA Takumi2012-08-301-1/+1
| | | | llvm-svn: 162915
* Reserve space for the mandatory traceback fields on PPC64.Hal Finkel2012-08-291-4/+8
| | | | | | | | | | | | | | | | | | | | | We need to reserve space for the mandatory traceback fields, though leaving them as zero is appropriate for now. Although the ABI calls for these fields to be filled in fully, no compiler on Linux currently does this, and GDB does not read these fields. GDB uses the first word of zeroes during exception handling to find the end of the function and the size field, allowing it to compute the beginning of the function. DWARF information is used for everything else. We need the extra 8 bytes of pad so the size field is found in the right place. As a comparison, GCC fills in a few of the fields -- language, number of saved registers -- but ignores the rest. IBM's proprietary OSes do make use of the full traceback table facility. Patch by Bill Schmidt. llvm-svn: 162854
* Emit word of zeroes after the last instruction as a start of the mandatoryRoman Divacky2012-08-281-0/+15
| | | | | | | | | | traceback table on PowerPC64. This helps gdb handle exceptions. The other mandatory fields are ignored by gdb and harder to implement so just add there a FIXME. Patch by Bill Schmidt. PR13641. llvm-svn: 162778
* Add PPC Freescale e500mc and e5500 subtargets.Hal Finkel2012-08-288-2/+609
| | | | | | | | | Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
* Split several PPC instruction classes.Hal Finkel2012-08-289-102/+269
| | | | | | | | | | | | | Slight reorganisation of PPC instruction classes for scheduling. No functionality change for existing subtargets. - Clearly separate load/store-with-update instructions from regular loads and stores. - Split IntRotateD -> IntRotateD and IntRotateDI - Split out fsub and fadd from FPGeneral -> FPAddSub - Update existing itineraries Patch by Tobias von Koch. llvm-svn: 162729
* Allow remat of LI on PPC.Hal Finkel2012-08-282-1/+3
| | | | | | | | | | | Allow load-immediates to be rematerialised in the register coalescer for PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail, because it relies on a register move getting emitted. The immediate load is equivalent, so change this test case. Patch by Tobias von Koch. llvm-svn: 162727
* Eliminate redundant CR moves on PPC32.Hal Finkel2012-08-283-8/+34
| | | | | | | | | | | | | | | | The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. llvm-svn: 162725
* Optimize zext on PPC64.Hal Finkel2012-08-281-0/+9
| | | | | | | | | | The zeroextend IR instruction is lowered to an 'and' node with an immediate mask operand, which in turn gets legalised to a sequence of ori's & ands. This can be done more efficiently using the rldicl instruction. Patch by Tobias von Koch. llvm-svn: 162724
* Fix integer undefined behavior due to signed left shift overflow in LLVM.Richard Smith2012-08-242-9/+8
| | | | | | Reviewed offline by chandlerc. llvm-svn: 162623
* Lower constant pools and jump tables via TOC on PPC64/SVR4.Roman Divacky2012-08-243-7/+40
| | | | | | In collaboration with Adhemerval Zanella. llvm-svn: 162562
* Add missing SDNPSideEffect flags.Jakob Stoklund Olesen2012-08-241-2/+4
| | | | llvm-svn: 162557
* Revert r162034, r162035 and r162037.Roman Divacky2012-08-162-20/+1
| | | | llvm-svn: 162039
* Define and handle additional fixup kinds. By Adhemerval Zanella.Roman Divacky2012-08-162-1/+20
| | | | llvm-svn: 162037
* Fix typo and grammar. By Adhemerval Zanella.Roman Divacky2012-08-161-1/+1
| | | | llvm-svn: 162032
* Don't use getNextOperandForReg().Jakob Stoklund Olesen2012-08-081-1/+4
| | | | | | | | | This way of using getNextOperandForReg() was unlikely to work as intended. We don't give any guarantees about the order of operands in the use-def chains, so looking only at operands following a given operand in the chain doesn't make sense. llvm-svn: 161542
* Add a comment about mftb vs. mfspr on PPC.Hal Finkel2012-08-071-0/+4
| | | | | | Thanks to Alex Rosenberg for the suggestion. llvm-svn: 161428
* MFTB on PPC64 should really be encoded using MFSPR.Hal Finkel2012-08-061-2/+2
| | | | | | | | | | | The MFTB instruction itself is being phased out, and its functionality is provided by MFSPR. According to the ISA docs, using MFSPR works on all known chips except for the 601 (which did not have a timebase register anyway) and the POWER3. Thanks to Adhemerval Zanella for pointing this out! llvm-svn: 161346
* Add readcyclecounter lowering on PPC64.Hal Finkel2012-08-042-1/+8
| | | | | | | | On PPC64, this can be done with a simple TableGen pattern. To enable this, I've added the (otherwise missing) readcyclecounter SDNode definition to TargetSelectionDAG.td. llvm-svn: 161302
* allow 'make CPPFLAGS=<something>' work againGabor Greif2012-08-031-1/+1
| | | | | | | | this makes this hack a bit more bearable for poor souls who need to pass custom preprocessor flags to the build process llvm-svn: 161240
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-132-20/+20
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189
* Target option DisableJumpTables is a gross hack. Move it to TargetLowering ↵Evan Cheng2012-07-022-16/+17
| | | | | | instead. llvm-svn: 159611
* Add all codegen passes to the PassManager via TargetPassConfig.Bob Wilson2012-07-021-3/+3
| | | | | | | | This is a preliminary step toward having TargetPassConfig be able to start and stop the compilation at specified passes for unit testing and debugging. No functionality change. llvm-svn: 159567
* Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp andBill Wendling2012-06-281-1/+1
| | | | | | | | | include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h. The reasoning is because the DebugInfo module is simply an interface to the debug info MDNodes and has nothing to do with analysis. llvm-svn: 159312
* There are a number of generic inline asm operand modifiers thatJack Carter2012-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | up to r158925 were handled as processor specific. Making them generic and putting tests for these modifiers in the CodeGen/Generic directory caused a number of targets to fail. This commit addresses that problem by having the targets call the generic routine for generic modifiers that they don't currently have explicit code for. For now only generic print operands 'c' and 'n' are supported.vi Affected files: test/CodeGen/Generic/asm-large-immediate.ll lib/Target/PowerPC/PPCAsmPrinter.cpp lib/Target/NVPTX/NVPTXAsmPrinter.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/XCore/XCoreAsmPrinter.cpp lib/Target/X86/X86AsmPrinter.cpp lib/Target/Hexagon/HexagonAsmPrinter.cpp lib/Target/CellSPU/SPUAsmPrinter.cpp lib/Target/Sparc/SparcAsmPrinter.cpp lib/Target/MBlaze/MBlazeAsmPrinter.cpp lib/Target/Mips/MipsAsmPrinter.cpp MSP430 isn't represented because it did not even run with the long existing 'c' modifier and it was not apparent what needs to be done to get it inline asm ready. Contributer: Jack Carter llvm-svn: 159203
* llvm/lib: [CMake] Add explicit dependency to intrinsics_gen.NAKAMURA Takumi2012-06-241-0/+2
| | | | llvm-svn: 159112
* Silence an unused variable warning on release builds.Craig Topper2012-06-231-2/+2
| | | | llvm-svn: 159074
* Add support for the PPC isel instruction.Hal Finkel2012-06-228-14/+84
| | | | | | | The isel (integer select) instruction is supported on the 440 and A2 embedded cores and on the POWER7. llvm-svn: 159045
* Convert the PPC backend to use the new FMA infrastructure.Hal Finkel2012-06-224-42/+48
| | | | | | | The existing contraction patterns are replaced with fma/fneg. Overall functionality should be the same. llvm-svn: 158955
* Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc ↵Hal Finkel2012-06-211-1/+6
| | | | | | | | stores on PPC. Thanks to Tobias von Koch for pointing out this problem. llvm-svn: 158932
* Add support for generating reg+reg (indexed) pre-inc loads on PPC.Hal Finkel2012-06-204-10/+106
| | | | llvm-svn: 158823
* Add DAG-combines for aggressive FMA formation.Lang Hames2012-06-191-1/+1
| | | | | | | | | | | | | | | | | | | | This patch adds DAG combines to form FMAs from pairs of FADD + FMUL or FSUB + FMUL. The combines are performed when: (a) Either AllowExcessFPPrecision option (-enable-excess-fp-precision for llc) OR UnsafeFPMath option (-enable-unsafe-fp-math) are set, and (b) TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) is true for the type of the FADD/FSUB, and (c) The FMUL only has one user (the FADD/FSUB). If your target has fast FMA instructions you can make use of these combines by overriding TargetLoweringInfo::isFMAFasterThanMulAndAdd(VT) to return true for types supported by your FMA instruction, and adding patterns to match ISD::FMA to your FMA instructions. llvm-svn: 158757
* Implement PPCInstrInfo::isCoalescableExtInstr().Jakob Stoklund Olesen2012-06-192-0/+19
| | | | | | | | | | | | | The PPC::EXTSW instruction preserves the low 32 bits of its input, just like some of the x86 instructions. Use it to reduce register pressure when the low 32 bits have multiple uses. This requires a small change to PeepholeOptimizer since EXTSW takes a 64-bit input register. This is related to PR5997. llvm-svn: 158743
* Mark most PPC register classes to avoid write-after-write.Hal Finkel2012-06-192-0/+16
| | | | | | | | | | | | | | | | | | | | | | | For processors with the G5-like instruction-grouping scheme, this helps avoid early group termination due to a write-after-write dependency within the group. It should also help on pipelined embedded cores. On POWER7, over the test suite, this gives an average 0.5% speedup. The largest speedups are: SingleSource/Benchmarks/Stanford/Quicksort - 33% MultiSource/Applications/d/make_dparser - 21% MultiSource/Benchmarks/FreeBench/analyzer/analyzer - 12% MultiSource/Benchmarks/MiBench/telecomm-FFT/telecomm-fft - 12% Largest slowdowns: SingleSource/Benchmarks/Stanford/Bubblesort - 23% MultiSource/Benchmarks/Prolangs-C++/city/city - 21% MultiSource/Benchmarks/BitBench/uuencode/uuencode - 16% MultiSource/Benchmarks/mediabench/mpeg2/mpeg2dec/mpeg2decode - 13% llvm-svn: 158719
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-196-25/+114
| | | | | | PPC will now generate STWUX and friends. llvm-svn: 158698
* Cleanup trip-count finding for PPC CTR loops (and some bug fixes).Hal Finkel2012-06-161-86/+127
| | | | | | | | | | | | | | This cleans up the method used to find trip counts in order to form CTR loops on PPC. This refactoring allows the pass to find loops which have a constant trip count but also happen to end with a comparison to zero. This also adds explicit FIXMEs to mark two different classes of loops that are currently ignored. In addition, we now search through all potential induction operations instead of just the first. Also, we check the predicate code on the conditional branch and abort the transformation if the code is not EQ or NE, and we then make sure that the branch to be transformed matches the condition register defined by the comparison (multiple possible comparisons will be considered). llvm-svn: 158607
* Add another missing 64-bit itinerary definition for the PPC A2 core.Hal Finkel2012-06-131-0/+11
| | | | llvm-svn: 158393
* Add some missing 64-bit itinerary definitions for the PPC A2 core.Hal Finkel2012-06-121-0/+22
| | | | llvm-svn: 158373
* Split out the PPC instruction class IntSimple from IntGeneral.Hal Finkel2012-06-129-65/+90
| | | | | | | On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. llvm-svn: 158366
* Fixes for PPC host detection and features.Hal Finkel2012-06-121-3/+3
| | | | | | | | | POWER4 is a 64-bit CPU (better matched to the 970). The g3 is really the 750 (no altivec), the g4+ is the 74xx (not the 750). Patch by Andreas Tobler. llvm-svn: 158363
* Reapply r158337, this time properly protect Darwin/PPC host CPU use with ↵Hal Finkel2012-06-121-135/+4
| | | | | | | | | | | | | __ppc__. Original commit message: Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName(). Both the new Linux functionality and the old Darwin functions have been moved. This change also allows this information to be queried directly by clang and other frontends (clang, for example, will now have real -mcpu=native support). llvm-svn: 158349
* Revert r158337 "Move PPC host-CPU detection logic from PPCSubtarget into ↵Jakob Stoklund Olesen2012-06-121-2/+133
| | | | | | | | | sys::getHostCPUName()." This commit broke most of the PowerPC unit tests when running on Intel/Apple. llvm-svn: 158345
* Move PPC host-CPU detection logic from PPCSubtarget into sys::getHostCPUName().Hal Finkel2012-06-111-133/+2
| | | | | | | | Both the new Linux functionality and the old Darwin functions have been moved. This change also allows this information to be queried directly by clang and other frontends (clang, for example, will now have real -mcpu=native support). llvm-svn: 158337
* Enable MFOCRF generation on the PPC A2 core.Hal Finkel2012-06-111-2/+2
| | | | llvm-svn: 158324
* Rename the PPC target feature gpul to mfocrf.Hal Finkel2012-06-115-13/+13
| | | | | | | | | | | The PPC target feature gpul (IsGigaProcessor) was only used for one thing: To enable the generation of the MFOCRF instruction. Furthermore, this instruction is available on other PPC cores outside of the G5 line. This feature now corresponds to the HasMFOCRF flag. No functionality change. llvm-svn: 158323
* Add A2 to the list of PPC CPUs recognized by Linux host CPU-type detection.Hal Finkel2012-06-111-0/+1
| | | | llvm-svn: 158322
* Emit the two-operand form of the PPC mfcr instruction as mfocrf.Hal Finkel2012-06-111-1/+1
| | | | | | This is necessary on Linux and supported on Darwin, see PR2604. llvm-svn: 158315
OpenPOWER on IntegriCloud