summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
* Fix the build bot break caused by rL261441.Nemanja Ivanovic2016-02-201-5/+11
| | | | | | | | The patch has a necessary call to a function inside an assert. Which is fine when you have asserts turned on. Not so much when they're off. Sorry about the regression. llvm-svn: 261447
* Fix for PR 26500Nemanja Ivanovic2016-02-202-52/+182
| | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D17294 It ensures that whatever block we are emitting the prologue/epilogue into, we have the necessary scratch registers. It takes away the hard-coded register numbers for use as scratch registers as registers that are guaranteed to be available in the function prologue/epilogue are not guaranteed to be available within the function body. Since we shrink-wrap, the prologue/epilogue may end up in the function body. llvm-svn: 261441
* Remove uses of builtin comma operator.Richard Trieu2016-02-182-22/+30
| | | | | | Cleanup for upcoming Clang warning -Wcomma. No functionality change intended. llvm-svn: 261270
* [PPCLoopDataPrefetch] Move pass to Transforms/Scalar/LoopDataPrefetch. NFCAdam Nemet2016-02-184-230/+1
| | | | | | | | | | | | | This patch is part of the work to make PPCLoopDataPrefetch target-independent (http://thread.gmane.org/gmane.comp.compilers.llvm.devel/92758). Obviously the pass still only used from PPC at this point. Subsequent patches will start driving this from ARM64 as well. Due to the previous patch most lines should show up as moved lines. llvm-svn: 261265
* [PPCLoopDataPrefetch] Remove PPC from some of the names. NFCAdam Nemet2016-02-181-14/+14
| | | | | | | | | | | | This is done only to make the next patch that move the pass out PPC to Transforms easier to read. After this most line should show up as moved lines in that patch. This patch is part of the work to make PPCLoopDataPrefetch target-independent (http://thread.gmane.org/gmane.comp.compilers.llvm.devel/92758). llvm-svn: 261264
* [CodeGen] Document and use getConstant's splat-building feature. NFC.Ahmed Bougacha2016-02-151-19/+6
| | | | | | Differential Revision: http://reviews.llvm.org/D17229 llvm-svn: 260901
* [MC] Merge VK_PPC_TPREL in to generic VK_TPREL.Colin LeMahieu2016-02-102-7/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D17038 llvm-svn: 260401
* Fix for PR 26193Nemanja Ivanovic2016-02-051-1/+1
| | | | | | | This is a simple fix for a PowerPC intrinsic that was incorrectly defined (the return type was incorrect). llvm-svn: 259886
* Fix for PR 26356Nemanja Ivanovic2016-02-041-5/+4
| | | | | | | | | Using the load immediate only when the immediate (whether signed or unsigned) can fit in a 16-bit signed field. Namely, from -32768 to 32767 for signed and 0 to 65535 for unsigned. This patch also ensures that we sign-extend under the right conditions. llvm-svn: 259840
* Fix for PR 26381Nemanja Ivanovic2016-02-031-1/+1
| | | | | | Simple fix - Constant values were not being sign extended in FastIsel. llvm-svn: 259645
* Codegen: [PPC] Fix PPCVSXFMAMutate to handle duplicates.Kyle Butt2016-02-031-19/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The purpose of PPCVSXFMAMutate is to elide copies by changing FMA forms on PPC. %vreg6<def> = COPY %vreg96 %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg5<kill>, %vreg7 ;v6 = v6 + v5 * v7 is replaced by %vreg5<def,tied1> = XSMADDMSP %vreg5<tied0>, %vreg7, %vreg96 ;v5 = v5 * v7 + v96 This was broken in the case where the target register was also used as a multiplicand. Fix this case by checking for it and replacing both uses with the copied register. %vreg6<def> = COPY %vreg96 %vreg6<def,tied1> = XSMADDASP %vreg6<tied0>, %vreg5<kill>, %vreg6 ;v6 = v6 + v5 * v6 is replaced by %vreg5<def,tied1> = XSMADDMSP %vreg5<tied0>, %vreg96, %vreg96 ;v5 = v5 * v96 + v96 llvm-svn: 259617
* Refactor common code for PPC fast isel load immediate selection.Eric Christopher2016-01-291-9/+5
| | | | llvm-svn: 259178
* Since LI/LIS sign extend the constant passed into the instruction we shouldEric Christopher2016-01-291-2/+3
| | | | | | | | | check that the sign extended constant fits into 16-bits if we want a zero extended value, otherwise go ahead and put it together piecemeal. Fixes PR26356. llvm-svn: 259177
* Fix up conditional formatting.Eric Christopher2016-01-291-5/+4
| | | | llvm-svn: 259176
* [TTI] Add getPrefetchDistance from PPCLoopDataPrefetch, NFCAdam Nemet2016-01-273-7/+12
| | | | | | | | | | | This patch is part of the work to make PPCLoopDataPrefetch target-independent (http://thread.gmane.org/gmane.comp.compilers.llvm.devel/92758). As it was discussed in the above thread, getPrefetchDistance is currently using instruction count which may change in the future. llvm-svn: 258995
* Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to ↵Benjamin Kramer2016-01-271-3/+3
| | | | | | | | CodeGen/ It's a SelectionDAG thing, not a Target thing. llvm-svn: 258939
* Move MCTargetAsmParser.h to llvm/MC/MCParser where it belongs.Benjamin Kramer2016-01-271-3/+3
| | | | llvm-svn: 258917
* Remove autoconf supportChris Bieneman2016-01-266-102/+0
| | | | | | | | | | | | | | | | Summary: This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html "I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened." - Obi Wan Kenobi Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D16471 llvm-svn: 258861
* Reflect the MC/MCDisassembler split on the include/ level.Benjamin Kramer2016-01-261-1/+1
| | | | | | No functional change, just moving code around. llvm-svn: 258818
* [TTI] Add getCacheLineSizeAdam Nemet2016-01-213-5/+16
| | | | | | | | | | | | | | | | | Summary: And use it in PPCLoopDataPrefetch.cpp. @hfinkel, please let me know if your preference would be to preserve the ppc-loop-prefetch-cache-line option in order to be able to override the value of TTI::getCacheLineSize for PPC. Reviewers: hfinkel Subscribers: hulx2000, mcrosier, mssimpso, hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D16306 llvm-svn: 258419
* GlobalValue: use getValueType() instead of getType()->getPointerElementType().Manuel Jacob2016-01-161-1/+1
| | | | | | | | | | | | Reviewers: mjacob Subscribers: jholewinski, arsenm, dsanders, dblaikie Patch by Eduard Burtescu. Differential Revision: http://reviews.llvm.org/D16260 llvm-svn: 257999
* Codegen: [PPC] Silence false-positive initialization warning. NFCKyle Butt2016-01-151-2/+2
| | | | | | | | | | Some compilers don't do exhaustive switch checking. For those compilers, add an initialization to prevent un-initialized variable warnings from firing. For compilers with exhaustive switch checking, we still get a guarantee that the switch is exhaustive, and hence the initializations are redundant, and a non-functional change. llvm-svn: 257923
* WebAssembly: fix build break introduced by ELFObjectWriter churnJF Bastien2016-01-131-1/+1
| | | | llvm-svn: 257709
* Convert a few assert failures into proper errors.Rafael Espindola2016-01-131-3/+3
| | | | | | Fixes PR25944. llvm-svn: 257697
* [PowerPC] Fix large code model with the ELFv2 ABIUlrich Weigand2016-01-133-24/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The global entry point prologue currently assumes that the TOC associated with a function is less than 2GB away from the function entry point. This is always true when using the medium or small code model, but may not be the case when using the large code model. This patch adds a new variant of the ELFv2 global entry point prologue that lifts the 2GB restriction when building with -mcmodel=large. This works by emitting a quadword containing the distance from the function entry point to its associated TOC immediately before the entry point, and then using a prologue like: ld r2,-8(r12) add r2,r2,r12 Since creation of the entry point prologue is now split across two separate routines (PPCLinuxAsmPrinter::EmitFunctionEntryLabel emits the data word, PPCLinuxAsmPrinter::EmitFunctionBodyStart the prolog code), I've switched to using named labels instead of just temporaries to indicate the locations of the global and local entry points and the new TOC offset data word. These names are provided by new routines in PPCFunctionInfo modeled after the existing PPCFunctionInfo::getPICOffsetSymbol. Note that a corresponding change was committed to GCC here: https://gcc.gnu.org/ml/gcc-patches/2015-12/msg00355.html Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D15500 llvm-svn: 257597
* Codegen: [PPC] Handle weighted comparisons when inserting selects.Kyle Butt2016-01-121-10/+33
| | | | | | | | | | | | | Only non-weighted predicates were handled in PPCInstrInfo::insertSelect. Handle the weighted predicates as well. This latent bug was triggered by r255398, because it added use of the branch-weighted predicates. While here, switch over an enum instead of an int to get the compiler to enforce totality in the future. llvm-svn: 257518
* Prevent renaming of CR fields in AADB when a CR restore is presentNemanja Ivanovic2016-01-082-2/+28
| | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D15930 Moves to and from CR fields depend on shifts/masks that depend on the target/source CR field. Thus, post-ra anti-dep breaking must not later change that CR register assignment. llvm-svn: 257168
* Add call sequence start and end for __tls_get_addrKyle Butt2016-01-081-0/+7
| | | | | | | | | | | | | | This is a fix for bug http://llvm.org/bugs/show_bug.cgi?id=25839. For a PIC TLS variable access in a function, prologue (mflr followed by std and stdu) gets scheduled after a tls_get_addr call. tls_get_addr messed up LR but no one saves/restores it. Also added a test for save/restore clobbered registers during calling __tls_get_addr. Patch by Tim Shen llvm-svn: 257137
* Refactor: Simplify boolean conditional return statements in lib/Target/PowerPCAlexander Kornienko2015-12-284-14/+4
| | | | | | | | | | | | | | Summary: Use clang-tidy to simplify boolean conditional return statements Reviewers: uweigand, rafael, wschmidt Subscribers: craig.topper, llvm-commits Patch by Richard Thomson! Differential Revision: http://reviews.llvm.org/D9984 llvm-svn: 256493
* Remove extra forward declarations and scrub includes for all in tree ↵Craig Topper2015-12-251-2/+0
| | | | | | InstPrinters. NFC llvm-svn: 256427
* [BPI] Replace weights by probabilities in BPI.Cong Hou2015-12-221-11/+9
| | | | | | | | | | | | This patch removes all weight-related interfaces from BPI and replace them by probability versions. With this patch, we won't use edge weight anymore in either IR or MC passes. Edge probabilitiy is a better representation in terms of CFG update and validation. Differential revision: http://reviews.llvm.org/D15519 llvm-svn: 256263
* Simplify. NFC.Rafael Espindola2015-12-171-6/+3
| | | | llvm-svn: 255894
* [CodeGen] Make MachineInstrBuilder::copyImplicitOps const. NFC.Ahmed Bougacha2015-12-161-13/+11
| | | | | | | | This matches the other MIB methods, none of which modify the builder. Without this, we can't chain copyImplicitOps. Also reformat the few users, in PPCEarlyReturn. llvm-svn: 255828
* LPM: Stop threading `Pass *` through all of the loop utility APIs. NFCJustin Bogner2015-12-152-2/+9
| | | | | | | | | | | | | | | | | | | | | | A large number of loop utility functions take a `Pass *` and reach into it to find out which analyses to preserve. There are a number of problems with this: - The APIs have access to pretty well any Pass state they want, so it's hard to tell what they may or may not do. - Other APIs have copied these and pass around a `Pass *` even though they don't even use it. Some of these just hand a nullptr to the API since the callers don't even have a pass available. - Passes in the new pass manager don't work like the current ones, so the APIs can't be used as is there. Instead, we should explicitly thread the analysis results that we actually care about through these APIs. This is both simpler and more reusable. llvm-svn: 255669
* Bitcasts between FP and INT values using direct movesNemanja Ivanovic2015-12-153-4/+41
| | | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D15286 This patch was meant to land in revision 255246, but I accidentally uploaded the patch that corresponds to http://reviews.llvm.org/D15372 in that revision accidentally. Thereby, this patch is the actual Bitcasts using direct moves patch, whereas http://reviews.llvm.org/rL255246 actually corresponds to http://reviews.llvm.org/D15372. llvm-svn: 255649
* Define a feature for __float128 support in the PPC back endNemanja Ivanovic2015-12-153-0/+7
| | | | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D15117 In preparation for supporting IEEE Quad precision floating point, this patch simply defines a feature to specify the target supports this. For now, nothing is done with the target feature, we just don't want warnings from the Clang FE when a user specifies -mfloat128. Calling convention and other related work will add to this patch in the near future. llvm-svn: 255642
* [Power PC] llvm soft float support for ppc32Petar Jovanovic2015-12-146-8/+32
| | | | | | | | | | | This is the second in a set of patches for soft float support for ppc32, it enables soft float operations. Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D13700 llvm-svn: 255516
* [PPC] Early exit loop. NFC.Chad Rosier2015-12-141-1/+4
| | | | llvm-svn: 255497
* Normalize MBB's successors' probabilities in several locations.Cong Hou2015-12-131-2/+2
| | | | | | | | | | | | This patch adds some missing calls to MBB::normalizeSuccProbs() in several locations where it should be called. Those places are found by checking if the sum of successors' probabilities is approximate one in MachineBlockPlacement pass with some instrumented code (not in this patch). Differential revision: http://reviews.llvm.org/D15259 llvm-svn: 255455
* [PowerPC] OutStreamer cleanup in PPCAsmPrinterHal Finkel2015-12-121-23/+19
| | | | | | | | We don't need to pass OutStreamer as a parameter to LowerSTACKMAP and LowerPATCHPOINT. It is a member variable of PPCAsmPrinter, and thus, is already available. NFC. llvm-svn: 255418
* [PowerPC] Add Branch Hints for Highly-Biased BranchesHal Finkel2015-12-122-2/+74
| | | | | | | | | | | This branch adds hints for highly biased branches on the PPC architecture. Even in absence of profiling information, LLVM will mark code reaching unreachable terminators and other exceptional control flow constructs as highly unlikely to be reached. Patch by Tom Jablin! llvm-svn: 255398
* Start replacing vector_extract/vector_insert with extractelt/inserteltMatt Arsenault2015-12-112-14/+14
| | | | | | | | | | | | | | | | | | | | These are redundant pairs of nodes defined for INSERT_VECTOR_ELEMENT/EXTRACT_VECTOR_ELEMENT. insertelement/extractelement are slightly closer to the corresponding C++ node name, and has stricter type checking so prefer it. Update targets to only use these nodes where it is trivial to do so. AArch64, ARM, and Mips all have various type errors on simple replacement, so they will need work to fix. Example from AArch64: def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8), (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>; Which is trying to do sext_inreg i8, i8. llvm-svn: 255359
* Fix build after r255319.Hans Wennborg2015-12-111-1/+1
| | | | llvm-svn: 255322
* [PPC]: Peephole optimize small accesss to aligned globals.Kyle Butt2015-12-111-9/+26
| | | | | | | | | | | | | | | | | | | | | | | Access to aligned globals gives us a chance to peephole optimize nonzero offsets. If a struct is 4 byte aligned, then accesses to bytes 0-3 won't overflow the available displacement. For example: addis 3, 2, b4v@toc@ha addi 4, 3, b4v@toc@l lbz 5, b4v@toc@l(3) ; This is the result of the current peephole lbz 6, 1(4) ; optimizer lbz 7, 2(4) lbz 8, 3(4) If b4v is 4-byte aligned, we can skip using register 4 because we know that b4v@toc@l+{1,2,3} won't overflow 32K, and instead generate: addis 3, 2, b4v@toc@ha lbz 4, b4v@toc@l(3) lbz 5, b4v@toc@l+1(3) lbz 6, b4v@toc@l+2(3) lbz 7, b4v@toc@l+3(3) Saving a register and an addition. Larger alignments allow larger structures/arrays to be optimized. llvm-svn: 255319
* PPC: Teach FMA mutate to respect register classes.Kyle Butt2015-12-101-2/+9
| | | | | | | | | This was causing bad code gen and assembly that won't assemble, as mixed altivec and vsx code would end up with a vsx high register assigned to an altivec instruction, which won't work. Constraining the classes allows the optimization to proceed. llvm-svn: 255299
* Bitcasts between FP and INT values using direct movesNemanja Ivanovic2015-12-101-90/+218
| | | | | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D15286 LLVM IR frequently contains bitcast operations between floating point and integer values of the same width. Doing this through memory operations is quite expensive on PPC. This patch allows the use of direct register moves between FPRs and GPRs for lowering bitcasts. llvm-svn: 255246
* [PPC64] Convert bool literals to i32Kit Barton2015-12-074-0/+261
| | | | | | | Convert i1 values to i32 values if they should be allocated in GPRs instead of CRs. Phabricator: http://reviews.llvm.org/D14064 llvm-svn: 254942
* Replace uint16_t with the MCPhysReg typedef in many places. A lot of ↵Craig Topper2015-12-052-3/+3
| | | | | | physical register arrays already use this typedef. llvm-svn: 254843
* [PowerPC] Remove wild call to RegScavenger::initRegState().Alexey Samsonov2015-12-021-2/+1
| | | | | | | | This call should in fact be made by RegScavenger::enterBasicBlock() called below. The first call does nothing except for triggering UB, indicated by UBSan (passing nullptr to memset()). llvm-svn: 254548
* Test Commit: iterateeKyle Butt2015-12-021-2/+2
| | | | | | Remove whitespace from blank lines. NFC llvm-svn: 254531
OpenPOWER on IntegriCloud