summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
* Move the post-lsr simplify cfg pass after lowereh, so it can clean up afterChris Lattner2005-09-271-2/+6
| | | | | | eh lowering as well. llvm-svn: 23459
* minor pattern shufflingChris Lattner2005-09-261-8/+3
| | | | llvm-svn: 23458
* Teach the dag isel generator how to construct arbitrary immediates. TheChris Lattner2005-09-241-1/+6
| | | | | | generated isel now tries li then lis, then lis+ori. llvm-svn: 23418
* Implement hook for ppcChris Lattner2005-09-172-0/+18
| | | | llvm-svn: 23374
* disable this for nowChris Lattner2005-09-151-0/+2
| | | | llvm-svn: 23366
* give all operands namesChris Lattner2005-09-141-3/+4
| | | | llvm-svn: 23356
* Fix some issues exposed by more testing. XORIS had the wrong operandsChris Lattner2005-09-141-5/+5
| | | | | | | specified. The various *imm operands defined by PPC are really all i32, even though the actual immediate is restricted to a smaller value in it. llvm-svn: 23352
* Fix some bugs noticed by new checking codeChris Lattner2005-09-141-8/+14
| | | | llvm-svn: 23350
* we don't need this proto any longerChris Lattner2005-09-131-1/+0
| | | | llvm-svn: 23342
* move the #include for the generated code into the isel class body so weChris Lattner2005-09-131-1/+3
| | | | | | can use/define class methods llvm-svn: 23339
* Change the arg lowering code to use copyfromreg from vregs associatedChris Lattner2005-09-131-12/+17
| | | | | | | | with incoming arguments instead of the pregs themselves. This fixes the scheduler from causing problems by moving a copyfromreg for an argument to after a select_cc node (now it can, and bad things won't happen). llvm-svn: 23334
* Remove some dead vectorsChris Lattner2005-09-131-4/+0
| | | | llvm-svn: 23329
* PowerPC cannot truncstore i1 nativelyChris Lattner2005-09-103-2/+3
| | | | llvm-svn: 23304
* I forgot that we always spill fp values as 64-bits. Implement spill foldingChris Lattner2005-09-091-3/+10
| | | | | | for FP as well. This triggers a couple dozen times on 177.mesa (for example). llvm-svn: 23299
* Fix a problem that Nate noticed, where spill code was not getting coallescedChris Lattner2005-09-092-0/+32
| | | | | | | | | | | | | | | | | | | | | with copies, leading to code like this: lwz r4, 380(r1) or r10, r4, r4 ;; Last use of r4 By teaching the PPC backend how to fold spills into copies, we now get this code: lwz r10, 380(r1) wow. :) This reduces a testcase nate sent me from 1505 instructions to 1484. Note that this could handle FP values but doesn't currently, for reasons mentioned in the patch llvm-svn: 23298
* code cleanupChris Lattner2005-09-091-2/+3
| | | | llvm-svn: 23297
* Teach the code generator that rlwimi is commutable if the rotate amountChris Lattner2005-09-093-1/+38
| | | | | | | | is zero. This lets the register allocator elide some copies in some cases. This implements CodeGen/PowerPC/rlwimi-commute.ll llvm-svn: 23292
* Introduce two new concepts:Chris Lattner2005-09-091-11/+75
| | | | | | | | | | | | | | 1. Add support for defining Pattern's, which can match expressions when there is no instruction that directly implements something. Instructions usually implicitly define patterns. 2. Add support for defining SDNodeXForm's, which are node transformations. This seperates the concept of a node xform out from the existing predicate support. Using this new stuff, we add a few instruction patterns, one for testing, and two for OR/XOR by an arbitrary immediate. llvm-svn: 23286
* whitespace/comment changes, no functionality diffsChris Lattner2005-09-081-2/+5
| | | | llvm-svn: 23283
* Add a bunch of stuff needed for node type inference. Move 'BLR' down withChris Lattner2005-09-081-21/+114
| | | | | | | the rest of the instructions, add comment markers to seperate portions of the file into logical parts llvm-svn: 23277
* add patterns for x?oris?Chris Lattner2005-09-082-8/+31
| | | | llvm-svn: 23268
* add patterns to the addi/addis/mulli etc instructions. Define predicatesChris Lattner2005-09-082-16/+52
| | | | | | for matching signed 16-bit and shifted 16-bit ppc immediates llvm-svn: 23267
* Add patterns for some new instructions, allowing the use of the ineg fragment.Chris Lattner2005-09-082-10/+10
| | | | llvm-svn: 23266
* Remove some cases handled by the generated portion of the iselChris Lattner2005-09-071-13/+3
| | | | llvm-svn: 23262
* On non-apple systems, when using -march=ppc32, do not print:Chris Lattner2005-09-071-1/+1
| | | | | | | | '' is not a recognized processor for this target (ignoring processor) Default to "generic" instead of "" for the default CPU. llvm-svn: 23257
* Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when weNate Begeman2005-09-064-13/+69
| | | | | | | | | are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. llvm-svn: 23250
* Add note about future optimization noted in the ppc compiler writer's guideNate Begeman2005-09-061-0/+4
| | | | llvm-svn: 23245
* Add accessor for 64bit flag, so that we can tell when it is safe toNate Begeman2005-09-062-1/+3
| | | | | | generate the fun in-register fp<->long instructions. llvm-svn: 23244
* explicitly specify an operands list for patterns with inputs (e.g. neg)Chris Lattner2005-09-031-8/+13
| | | | llvm-svn: 23240
* include the dag isel fragmentChris Lattner2005-09-031-0/+2
| | | | llvm-svn: 23239
* ask for a dag iselChris Lattner2005-09-031-1/+2
| | | | llvm-svn: 23238
* Change the isel to not break out of the big giant switch. Instead, theChris Lattner2005-09-031-59/+61
| | | | | | switch should never be exited, so its bottom is now unreachable. llvm-svn: 23234
* rearrange logical ops to group them together more consistently.Chris Lattner2005-09-031-16/+42
| | | | | | | | Define the PatFrag class which can be used to define subpatterns to match things with. Define 'not', and use it to define the patterns for andc, nand, etc. llvm-svn: 23233
* Add AND/OR/XORChris Lattner2005-09-022-31/+65
| | | | llvm-svn: 23232
* Add some initial patterns to simple binary instructions, though theyChris Lattner2005-09-022-25/+43
| | | | | | | | | currently don't do anything. This elides patterns for binary operators that ping on the carry flag, since we don't model it yet. This patch also removes PPC::SUB, because it is dead. llvm-svn: 23230
* turn on dag isel by defaultChris Lattner2005-09-021-3/+3
| | | | llvm-svn: 23226
* Add help support for -mcpu and -mattr.Jim Laskey2005-09-021-21/+27
| | | | llvm-svn: 23222
* Decouple fsqrt from gpul optimizations, implementing fsqrt.ll.Chris Lattner2005-09-023-8/+8
| | | | | | Remove the -enable-gpopt option which is subsumed by feature flags. llvm-svn: 23218
* Restore this patch now that the latent bug has been fixedChris Lattner2005-09-021-2/+16
| | | | llvm-svn: 23209
* Revert the previous patch which causes a mysterious regression in toast.Chris Lattner2005-09-021-16/+2
| | | | llvm-svn: 23207
* Implement small-arguments.ll:test3 by teaching the DAG optimizer thatChris Lattner2005-09-011-2/+16
| | | | | | | the results of calls to functions returning small values are properly sign/zero extended. llvm-svn: 23198
* Align functions to 16-byte boundaries, to eliminate noise in performance ↵Chris Lattner2005-09-011-1/+1
| | | | | | | | measurements. This improves the performance of 'treeadd' by about 20% with the dag isel, restoring it to the pattern-isel level (which happens to get the alignment right). llvm-svn: 23194
* Local labels on darwin apparently start with just 'L', not .L like otherChris Lattner2005-09-011-2/+2
| | | | | | | platforms. This reduces executable size and makes shark realize the actual bounds of functions instead of showing each MBB as a function :) llvm-svn: 23193
* 1. Use SubtargetFeatures in llc/lli.Jim Laskey2005-09-015-16/+94
| | | | | | | | 2. Propagate feature "string" to all targets. 3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget. llvm-svn: 23192
* Implement dynamic allocas correctly. In particular, because we were copyingChris Lattner2005-09-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | directly out of R1 (without using a CopyFromReg, which uses a chain), multiple allocas were getting CSE'd together, producing bogus code. For this: int %foo(bool %X, int %A, int %B) { br bool %X, label %T, label %F F: %G = alloca int %H = alloca int store int %A, int* %G store int %B, int* %H %R = load int* %G ret int %R T: ret int 0 } We were generating: _foo: stwu r1, -16(r1) stw r31, 4(r1) or r31, r1, r1 stw r1, 12(r31) cmpwi cr0, r3, 0 bne cr0, .LBB_foo_2 ; T .LBB_foo_1: ; F li r2, 16 subf r2, r2, r1 ;; One alloca or r1, r2, r2 or r3, r1, r1 or r1, r2, r2 or r2, r1, r1 stw r4, 0(r3) stw r5, 0(r2) lwz r3, 0(r3) lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr .LBB_foo_2: ; T li r3, 0 lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr Now we generate: _foo: stwu r1, -16(r1) stw r31, 4(r1) or r31, r1, r1 stw r1, 12(r31) cmpwi cr0, r3, 0 bne cr0, .LBB_foo_2 ; T .LBB_foo_1: ; F or r2, r1, r1 li r3, 16 subf r2, r3, r2 ;; Alloca 1 or r1, r2, r2 or r2, r1, r1 or r6, r1, r1 subf r3, r3, r6 ;; Alloca 2 or r1, r3, r3 or r3, r1, r1 stw r4, 0(r2) stw r5, 0(r3) lwz r3, 0(r2) lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr .LBB_foo_2: ; T li r3, 0 lwz r1, 12(r31) lwz r31, 4(r31) lwz r1, 0(r1) blr This fixes Povray and SPASS with the dag isel, the last two failing cases. Tommorow we will hopefully turn it on by default! :) llvm-svn: 23190
* Fix a bug where we were useing HA to get the high part, which seems like itChris Lattner2005-09-011-11/+10
| | | | | | | | | | could cause a miscompile. Fixing this didn't fix the two programs that fail though. :( This also changes the implementation to follow the pattern selector more closely, causing us to select 0 to li instead of lis. llvm-svn: 23189
* Do not select the operands being passed into SelectCC. IT does this itselfChris Lattner2005-09-011-4/+2
| | | | | | and selecting early prevents folding immediates into the cmpw* instructions llvm-svn: 23188
* Move FCTIWZ handling out of the instruction selectors and into legalization,Chris Lattner2005-08-314-64/+70
| | | | | | getting them out of the business of making stack slots. llvm-svn: 23180
* Remove dead codeChris Lattner2005-08-312-75/+0
| | | | llvm-svn: 23179
* Move SHL,SHR i64 -> legalizerChris Lattner2005-08-311-2/+57
| | | | llvm-svn: 23178
OpenPOWER on IntegriCloud