summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC
Commit message (Collapse)AuthorAgeFilesLines
...
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-2514-97/+57
| | | | llvm-svn: 135942
* Set PPCII::MO_DARWIN_STUB only on MacOSX < 10.5.Roman Divacky2011-07-241-2/+2
| | | | llvm-svn: 135866
* Move TargetAsmParser.h TargetAsmBackend.h and TargetAsmLexer.h to MC where ↵Evan Cheng2011-07-231-1/+1
| | | | | | they belong. llvm-svn: 135833
* createXXXMCCodeGenInfo should be static.Evan Cheng2011-07-231-2/+2
| | | | llvm-svn: 135826
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-221-23/+20
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-203-13/+17
| | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. llvm-svn: 135580
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-193-36/+39
| | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. llvm-svn: 135468
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-184-15/+16
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-183-33/+19
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-182-8/+8
| | | | llvm-svn: 135375
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-151-0/+4
| | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. llvm-svn: 135237
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-146-18/+22
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-1410-44/+116
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Most MCCodeEmitter's don't meed MCContext.Evan Cheng2011-07-111-3/+1
| | | | llvm-svn: 134922
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-114-9/+26
| | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. llvm-svn: 134884
* Change createAsmParser to take a MCSubtargetInfo instead of triple,Evan Cheng2011-07-091-0/+15
| | | | | | | | | CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. llvm-svn: 134795
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+2
| | | | | | is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-082-2/+3
| | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". llvm-svn: 134678
* Compute feature bits at time of MCSubtargetInfo initialization.Evan Cheng2011-07-072-4/+4
| | | | llvm-svn: 134606
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-062-5/+2
| | | | llvm-svn: 134525
* Remove accidentaly left node from previous iteration of the patch.Roman Divacky2011-07-041-3/+0
| | | | | | Noticed by Benjamin Kramer! llvm-svn: 134376
* Make the i64 and f64 be 64bit ABI aligned in the target description.Roman Divacky2011-07-031-1/+1
| | | | | | This is what both the ABI and clang says. llvm-svn: 134367
* Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.Evan Cheng2011-07-014-4/+4
| | | | llvm-svn: 134281
* Rename TargetSubtarget to TargetSubtargetInfo for consistency.Evan Cheng2011-07-012-3/+3
| | | | llvm-svn: 134259
* - Added MCSubtargetInfo to capture subtarget features and schedulingEvan Cheng2011-07-012-3/+15
| | | | | | | | | itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. llvm-svn: 134257
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-012-3/+6
| | | | llvm-svn: 134244
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-304-14/+21
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-291-3/+2
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-282-4/+4
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-284-5/+7
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-282-9/+9
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Implement ISD::VAARG lowering on PPC32.Roman Divacky2011-06-281-5/+123
| | | | llvm-svn: 134005
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-275-9/+9
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Refactor MachO relocation generaration into the Target directories.Jim Grosbach2011-06-241-0/+6
| | | | | | | | | Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. llvm-svn: 133844
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-243-5/+8
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflowRoman Divacky2011-06-201-14/+23
| | | | | | with 32bit values. llvm-svn: 133439
* Fix a few places where 32bit instructions/registerset were used on PPC64.Roman Divacky2011-06-172-4/+13
| | | | llvm-svn: 133260
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-33/+26
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105
* Make PPC64CompilationCallback compilable no non-darwin platforms.Roman Divacky2011-06-151-34/+56
| | | | | | Patch by Nathan Whitehorn! llvm-svn: 133059
* PR10136: fix PPCTargetLowering::LowerCall_SVR4 so that a necessary CopyToReg ↵Eli Friedman2011-06-141-7/+6
| | | | | | | | doesn't appear to be dead. Roman, since you're writing tests for other PPC-SVR4 vararg-related stuff, would you mind writing a test for this? llvm-svn: 133018
* Fix emission of PPC64 assembler on non-darwin platforms by splittingRoman Divacky2011-06-093-11/+12
| | | | | | | | VK_PPC_{HA,LO}16 into darwin and gas variants. Darwin wants {ha,lo}16(symbol) while gnu as wants symbol@{ha,l}. llvm-svn: 132802
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-59/+3
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. llvm-svn: 132781
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-17/+17
| | | | | | | | No functional change. Part of PR6965 llvm-svn: 132763
* Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.Roman Divacky2011-06-034-6/+12
| | | | | | | | | | | | | - Check for MTCTR8 in addition to MTCTR when looking up a hazard. - When lowering an indirect call use CTR8 when targeting 64bit. - Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND. The last change fixes PR8487. With those changes, we are able to compile a running "ls" and "sh" on FreeBSD/PowerPC64. llvm-svn: 132552
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-022-3/+9
| | | | | | Part of rdar://9119939 llvm-svn: 132510
* Don't hardcode the %reg format in the streamer.Rafael Espindola2011-06-022-3/+3
| | | | llvm-svn: 132451
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-305-0/+21
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-302-141/+152
| | | | llvm-svn: 132315
* Dwarf register 0 is r0, remove incorrect entries.Rafael Espindola2011-05-291-2/+2
| | | | llvm-svn: 132276
OpenPOWER on IntegriCloud