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* [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual registerKai Luo2019-08-021-0/+6
| | | | | | | | | | | Summary: When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check if `extsw`'s second operand is a virtual register, otherwise we might get miscompile. Differential Revision: https://reviews.llvm.org/D65315 llvm-svn: 367645
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to ↵Daniel Sanders2019-08-019-47/+46
| | | | | | llvm::Register as started by r367614. NFC llvm-svn: 367633
* recommit:[PowerPC] Eliminate loads/swap feeding swap/store for vector type ↵Zi Xuan Wu2019-08-013-1/+117
| | | | | | | | | | | | by using big-endian load/store In PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. So we can combine vector load + reverse into big endian load to eliminate the swap instruction. Also combine vector reverse + store into big endian store. Differential Revision: https://reviews.llvm.org/D65063 llvm-svn: 367516
* revert r367382 because buildbot failureZi Xuan Wu2019-07-313-116/+1
| | | | llvm-svn: 367388
* [PowerPC] Eliminate loads/swap feeding swap/store for vector type by using ↵Zi Xuan Wu2019-07-313-1/+116
| | | | | | | | | | big-endian load/store In PowerPC, there is instruction to load vector in big endian element order when it's in little endian target. So we can combine vector load + reverse into big endian load to eliminate the swap instruction. Also combine vector reverse + store into big endian store. llvm-svn: 367382
* Address post commit review comments on revision 366727.Sean Fertile2019-07-301-5/+5
| | | | | | | | | | | | | Addresses number of comment made on D64652 after commiting: - Reorders function decls in the TargetLoweringObjectFileXCOFF class. - Fix comment in MCSectionXCOFF to include description of external reference csects. - Convert several llvm_unreachables to report_fatal_error - Convert several dyn_casts to casts as they are expected not to fail. - Avoid copying DataLayout object. llvm-svn: 367324
* [PowerPC][NFC]Fix a typo in comment.Jinsong Ji2019-07-291-1/+1
| | | | llvm-svn: 367252
* [PowerPC][AIX]Add lowering of MCSymbol MachineOperand.Sean Fertile2019-07-261-0/+3
| | | | | | | | | | | Adds machine operand lowering for MCSymbolSDNodes to the PowerPC backend. This is needed to produce call instructions in assembly for AIX because the callee operand is a MCSymbolSDNode. The test is XFAIL'ed for asserts due to a (valid) assertion in PEI that the AIX ABI isn't supported yet. Differential Revision: https://reviews.llvm.org/D63738 llvm-svn: 367133
* [PowerPC] Add getCRSaveOffset to improve readability. [NFC]Sean Fertile2019-07-262-6/+17
| | | | | | | | | | In preperation for AIX support in FrameLowering: replace a number of literal '8' that represent the stack offset of the condition register save area with a member in PPCFrameLowering. Patch by Chris Bowler. llvm-svn: 367111
* [PowerPC][NFC] Make `getDefMIPostRA` publicKai Luo2019-07-251-5/+5
| | | | llvm-svn: 366995
* [PowerPC][NFC] Added `getDefMIPostRA` methodKai Luo2019-07-252-21/+38
| | | | | | | | | | | Summary: In PostRA phase, we often have to find out the most recent definition of a register. This patch adds getDefMIPostRA so that other methods can use it rather than implementing it repeatedly. Differential Revision: https://reviews.llvm.org/D65131 llvm-svn: 366990
* [PowerPC][NFC] use opcode instead of MachineInstr for instrHasImmForm().Chen Zheng2019-07-242-9/+14
| | | | llvm-svn: 366867
* [PowerPC] Remove redundant load immediate instructionsYi-Hong Lyu2019-07-231-0/+103
| | | | | | | | | | | | | | | | | | | Currently PowerPC backend emits code like this: r3 = li 0 std r3, 264(r1) r3 = li 0 std r3, 272(r1) This patch fixes that and other cases where a register already contains a value that is loaded so we will get: r3 = li 0 std r3, 264(r1) std r3, 272(r1) Differential Revision: https://reviews.llvm.org/D64220 llvm-svn: 366840
* [PowerPC] Replace float load/store pair with integer load/store pair when ↵Zi Xuan Wu2019-07-231-0/+12
| | | | | | | | | | | | | | it's only used in load/store Replace float load/store pair with integer load/store pair when it's only used in load/store, because float load/store instructions cost more cycles then integer load/store. A typical scenario is when there is a call with more than 13 float arguments passing, we need pass them by stack. So we need a load/store pair to do such memory operation if the variable is global variable. Differential Revision: https://reviews.llvm.org/D64195 llvm-svn: 366775
* [NFC][PowerPC]Change ADDIStocHA to ADDIStocHA8 to follow 64-bit naming ↵Jason Liu2019-07-227-19/+19
| | | | | | | | | | | | | | | convention Summary: Since we are planning to add ADDIStocHA for 32bit in later patch, we decided to change 64bit one first to follow naming convention with 8 behind opcode. Patch by: Xiangling_L Differential Revision: https://reviews.llvm.org/D64814 llvm-svn: 366731
* Stubs out TLOF for AIX and add support for common vars in assembly output.Sean Fertile2019-07-222-2/+36
| | | | | | | | | Stubs out a TargetLoweringObjectFileXCOFF class, implementing only SelectSectionForGlobal for common symbols. Also adds an override of EmitGlobalVariable in PPCAIXAsmPrinter which adds a number of defensive errors and adds support for emitting common globals. llvm-svn: 366727
* [PowerPC] Fix comment on MO_PLT Target Operand Flag. [NFC]Sean Fertile2019-07-221-2/+2
| | | | | | Patch by Xiangling Liao. llvm-svn: 366724
* PowerPC: Fix register spilling for SPE registersJustin Hibbits2019-07-173-25/+47
| | | | | | | | | | | | | | | | | | Summary: Missed in the original commit, use the correct callee-saved register list for spilling, instead of the standard SVR432 list. This avoids needlessly spilling the SPE non-volatile registers when they're not used. As part of this, also add where missing, and sort, the spill opcode checks for SPE and SPE4 register classes. Reviewers: nemanjai, hfinkel, joerg Subscribers: kbarton, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D56703 llvm-svn: 366319
* PowerPC/SPE: Fix load/store handling for SPEJustin Hibbits2019-07-173-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Pointed out in a comment for D49754, register spilling will currently spill SPE registers at almost any offset. However, the instructions `evstdd` and `evldd` require a) 8-byte alignment, and b) a limit of 256 (unsigned) bytes from the base register, as the offset must fix into a 5-bit offset, which ranges from 0-31 (indexed in double-words). The update to the register spill test is taken partially from the test case shown in D49754. Additionally, pointed out by Kei Thomsen, globals will currently use evldd/evstdd, though the offset isn't known at compile time, so may exceed the 8-bit (unsigned) offset permitted. This fixes that as well, by forcing it to always use evlddx/evstddx when accessing globals. Part of the patch contributed by Kei Thomsen. Reviewers: nemanjai, hfinkel, joerg Subscribers: kbarton, jsji, llvm-commits Differential Revision: https://reviews.llvm.org/D54409 llvm-svn: 366318
* [PowerPC][HTM] Fix impossible reg-to-reg copy assert with ttest builtinJinsong Ji2019-07-161-1/+3
| | | | | | | | | | | | | | | | | | | | Summary: This is exposed by our internal testing. The reduced testcase will assert with "Impossible reg-to-reg copy" We can't use COPY to do 32-bit to 64-bit conversion. Reviewers: kbarton, hfinkel, nemanjai Reviewed By: hfinkel Subscribers: hiraditya, MaskRay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64499 llvm-svn: 366255
* Delete dead storesFangrui Song2019-07-121-7/+5
| | | | llvm-svn: 365903
* [NFC]Fix IR/MC depency issue for function descriptor SDAG implementationDavid Tenty2019-07-101-44/+35
| | | | | | | | | | | | | | | | | | Summary: llvm/IR/GlobalValue.h can't be included in MC, that creates a circular dependency between MC and IR libraries. This circular dependency is causing an issue for build system that enforce layering. Author: Xiangling_L Reviewers: sfertile, jasonliu, hubert.reinterpretcast, gribozavr Reviewed By: gribozavr Subscribers: wuzish, nemanjai, hiraditya, kbarton, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64445 llvm-svn: 365701
* Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"David Greene2019-07-102-4/+4
| | | | | | | | This broke some PPC prefetching tests. This reverts commit 9fdfb045ae8bb643ab0d0455dcf9ecaea3b1eb3c. llvm-svn: 365680
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-07-102-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the TTI cache and software prefetching APIs to prepare for the introduction of a general system model. Changes include: - Marking existing interfaces const and/or override as appropriate - Adding comments - Adding BasicTTIImpl interfaces that delegate to a subtarget implementation - Adding a default "no information" subtarget implementation Only a handful of targets use these interfaces currently: AArch64, Hexagon, PPC and SystemZ. AArch64 already has a custom subtarget implementation, so its custom TTI implementation is migrated to use the new facilities in BasicTTIImpl to invoke its custom subtarget implementation. The custom TTI implementations continue to exist for the other targets with this change. They are not moved over to subtarget-based implementations. The end goal is to have the default subtarget implementation defer to the system model defined by the target. With this change, the default subtarget implementation essentially returns "no information" for these interfaces. None of the existing users of TTI will hit that implementation because they define their own custom TTI implementations and won't use the BasicTTIImpl implementations. Once system models are in place for the targets that use these interfaces, their custom TTI implementations can be removed. Differential Revision: https://reviews.llvm.org/D63614 llvm-svn: 365676
* Boilerplate for producing XCOFF object files from the PowerPC backend.Sean Fertile2019-07-098-1/+98
| | | | | | | | | | Stubs out a number of the classes needed to produce a new object file format (XCOFF) for the powerpc-aix target. For testing input is an empty module which produces an object file with just a file header. Differential Revision: https://reviews.llvm.org/D61694 llvm-svn: 365541
* [NFC][PowerPC] Fixed unused variable 'NewInstr'.Kai Luo2019-07-091-0/+1
| | | | llvm-svn: 365433
* [PowerPC][Peephole] Combine extsw and sldi after instruction selectionKai Luo2019-07-093-7/+86
| | | | | | | | | | | Summary: `extsw` and `sldi` are supposed to be combined if they are in the same BB in instruction selection phase. This patch handles the case where extsw and sldi are not in the same BB. Differential Revision: https://reviews.llvm.org/D63806 llvm-svn: 365430
* [PowerPC][NFC] remove redundant function isVFReg().Chen Zheng2019-07-091-8/+4
| | | | llvm-svn: 365429
* [PowerPC] Fold another unused variable into assertion. NFC.Benjamin Kramer2019-07-051-2/+2
| | | | llvm-svn: 365237
* [PowerPC] Fold variable into assert. NFC.Benjamin Kramer2019-07-051-2/+1
| | | | | | Avoids a warning in Release builds. llvm-svn: 365236
* [PowerPC] Remove unused variable. NFC.Benjamin Kramer2019-07-051-1/+0
| | | | llvm-svn: 365235
* [PowerPC] Move TOC save to prologue when profitableNemanja Ivanovic2019-07-053-0/+87
| | | | | | | | | | | | | | | | | | | | | The indirect call sequence on PPC requires that the TOC base register be saved prior to the indirect call and restored after the call since the indirect call may branch to a global entry point in another DSO which will update the TOC base. Over the last couple of years, we have improved this to: - be able to hoist TOC saves from loops (with changes to MachineLICM) - avoid multiple saves when one dominates the other[s] However, it is still possible to have multiple TOC saves dynamically in the execution path if there is no dominance relationship between them. This patch moves the TOC save to the prologue when one of the TOC saves is in a block that post-dominates entry (i.e. it cannot be avoided) or if it is in a block that is hotter than entry. Differential revision: https://reviews.llvm.org/D63803 llvm-svn: 365232
* [NFC][PowerPC] Make the PowerPC scheduling strategy feature only control the ↵QingShan Zhang2019-07-041-10/+10
| | | | | | strategy instead of the scheduler. llvm-svn: 365110
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-4/+6
| | | | | | | | | | | | | Summary: "ww" and "ws" are both constraint codes for VSX vector registers that hold scalar double data. "ww" is preferred for float while "ws" is preferred for double. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D64119 llvm-svn: 365106
* [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)Roman Lebedev2019-07-032-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]. In middle-end, we'd want to prefer the form with two adds - D63992, but as this diff shows, not every target will prefer that pattern. Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars, but only X86 prefer that same pattern for vectors. Here i'm adding a new TLI hook, always defaulting to the inc-of-add, but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars. Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel Reviewed By: efriedma Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64090 llvm-svn: 365010
* [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware ↵Chen Zheng2019-07-032-0/+25
| | | | | | | | | loop. Differential Revision: https://reviews.llvm.org/D63477 llvm-svn: 364993
* [PowerPC] Implement the areMemAccessesTriviallyDisjoint hookQingShan Zhang2019-07-022-0/+72
| | | | | | | | | After implemented this hook, we will model the memory dependency in the scheduling dependency graph more precise, and will have more opportunity to reorder the load/stores, as they didn't have the dependency at some condition Differential Revision: https://reviews.llvm.org/D63804 llvm-svn: 364886
* Revert Recommit [PowerPC] Update P9 vector costs for insert/extract elementJordan Rupprecht2019-07-011-29/+0
| | | | | | | | This reverts r364557 (git commit 9f7f5858fe46b8e706e87a83e2fd0a2678be619e) This crashes as reported on the commit thread. Repro instructions TBD. llvm-svn: 364876
* Default to Secure PLT on PPC for musl libc.Brad Smith2019-06-281-1/+2
| | | | | | This matches the default settings of clang. llvm-svn: 364675
* [NFC][PowerPC] Move XS*QP series instruction apart from XS*QPO series in ↵Zi Xuan Wu2019-06-281-33/+33
| | | | | | position of td file llvm-svn: 364620
* [PowerPC][NFC] Use `|=` to update `Simplified` flagKai Luo2019-06-281-1/+1
| | | | llvm-svn: 364617
* [PowerPC][NFC] Remove unused (and unsupported) fusion feature bits.Jinsong Ji2019-06-273-7/+1
| | | | | | | | | | | | | | | FeatureFusion bits was first introduced in https://reviews.llvm.org/rL253724. for add/load integer fusion for P8. The only use of `hasFusion` was https://reviews.llvm.org/rL255319. However, this was removed later in https://reviews.llvm.org/rL280440. So, there is NO any reference to fusion in code now. Leaving it there is misleading and confusing, so remove it for now. We can alwasy add back if we ever support fusion in the future. llvm-svn: 364581
* Recommit [PowerPC] Update P9 vector costs for insert/extract elementRoland Froese2019-06-271-0/+29
| | | | | | Recommit patch D60160 after regression fix patch D63463. llvm-svn: 364557
* [PowerPC][HTM] Fix disassembling buffer overflow for tabortdc and othersJinsong Ji2019-06-275-33/+28
| | | | | | | | | | | | | | | | | This was reported in https://bugs.llvm.org/show_bug.cgi?id=41751 llvm-mc aborted when disassembling tabortdc. This patch try to clean up TM related DAGs. * Fixes the problem by remove explicit output of cr0, and put it as implicit def. * Update int_ppc_tbegin pattern to accommodate the implicit def of cr0. * Update the TCHECK operand and int_ppc_tcheck accordingly. * Add some builtin test and disassembly tests. * Remove unused CRRC0/crrc0 Differential Revision: https://reviews.llvm.org/D61935 llvm-svn: 364544
* [NFC][PowerPC] Improve the for loop in Early ReturnKang Zhang2019-06-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In `PPCEarlyReturn.cpp` ``` 183 for (MachineFunction::iterator I = MF.begin(); I != MF.end();) { 184 MachineBasicBlock &B = *I++; 185 if (processBlock(B)) 186 Changed = true; 187 } ``` Above code can be improved to: ``` 184 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E;) { 185 MachineBasicBlock &B = *I++; 186 Changed |= processBlock(B); 187 } ``` Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D63800 llvm-svn: 364496
* [PowerPC] Fixed missing change flag of emitRLDICWhenLoweringJumpTablesKai Luo2019-06-261-9/+10
| | | | | | | | | PPCMIPeephole::emitRLDICWhenLoweringJumpTables should return a bool value to indicate optimization is conducted or not. Differential Revision: https://reviews.llvm.org/D63801 llvm-svn: 364383
* [PowerPC] Mark FCOPYSIGN legal for FP vectorsNemanja Ivanovic2019-06-261-0/+2
| | | | | | | | | | This was just an omission in the back end. We have had the instructions for both single and double precision for a few HW generations, but never got around to legalizing these. Differential revision: https://reviews.llvm.org/D63634 llvm-svn: 364373
* [PowerPC][NFC] Move peephole optimization of RLDICR into a method.Kai Luo2019-06-261-47/+57
| | | | llvm-svn: 364372
* [PPC32] Support PLT calls for -msecure-plt -fpicFangrui Song2019-06-253-34/+30
| | | | | | | | | | | | | | | | | | | | Summary: In Secure PLT ABI, -fpic is similar to -fPIC. The differences are that: * -fpic stores the address of _GLOBAL_OFFSET_TABLE_ in r30, while -fPIC stores .got2+0x8000. * -fpic uses an addend of 0 for R_PPC_PLTREL24, while -fPIC uses 0x8000. Reviewers: hfinkel, jhibbits, joerg, nemanjai, spetrovic Reviewed By: jhibbits Subscribers: adalava, kbarton, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63563 llvm-svn: 364324
* [PowerPC] Emit XXSEL for vec_sel and code that has the same patternNemanja Ivanovic2019-06-251-0/+4
| | | | | | | | | | As pointed out in https://bugs.llvm.org/show_bug.cgi?id=41777 we do not emit a vector select even when the pretty much asks for one. This patch changes that. Differential revision: https://reviews.llvm.org/D61658 llvm-svn: 364289
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