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path: root/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
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* implement proper PPC64 prolog/epilog codegen.Chris Lattner2006-11-111-30/+76
| | | | llvm-svn: 31684
* Running with frame pointers prevented debugging, external probes andJim Laskey2006-11-111-2/+5
| | | | | | | | potentially some system calls/exception handling from working. TOS must always link to previous frame. This is a short term workaround until alloca scheme is reworked. llvm-svn: 31677
* For PR786:Reid Spencer2006-11-021-1/+0
| | | | | | | | | | Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting fall out by removing unused variables. Remaining warnings have to do with unused functions (I didn't want to delete code without review) and unused variables in generated code. Maintainers should clean up the remaining issues when they see them. All changes pass DejaGnu tests and Olden. llvm-svn: 31380
* Completely eliminate def&use operands. Now a register operand is EITHER aChris Lattner2006-09-051-3/+3
| | | | | | def operand or a use operand. llvm-svn: 30109
* Handle callee saved registers in dwarf frame info (lead up to exceptionJim Laskey2006-08-291-6/+13
| | | | | | handling.) llvm-svn: 29954
* Fix some comments.Jim Laskey2006-08-251-1/+4
| | | | llvm-svn: 29880
* The PPC64 JIT needs register numbers to encode instructions.Chris Lattner2006-07-111-35/+36
| | | | llvm-svn: 29114
* In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.Chris Lattner2006-07-111-59/+94
| | | | llvm-svn: 29096
* Fix rewriting frame offsets with ixaddr instructions, which implicitly shiftChris Lattner2006-06-271-8/+21
| | | | | | the offset two bits to the left. llvm-svn: 28933
* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-3/+3
| | | | llvm-svn: 28889
* Gaar! Don't use r11 for CR save/restore, use R0. R11 can be registerChris Lattner2006-06-121-9/+11
| | | | | | | | | | | | | | | | | | | allocated, thus live across the save/reload. This fixes llc-beta /MultiSource/Applications/spiff/spiff llc-beta /MultiSource/Benchmarks/sim/sim: llc-beta /MultiSource/Benchmarks/Ptrdist/bc/bc llc-beta /MultiSource/Benchmarks/McCat/12-IOtest/iotest: llc-beta /MultiSource/Benchmarks/FreeBench/fourinarow/fourinarow llc-beta /MultiSource/Benchmarks/Fhourstones-3.1/fhourstones3.1 llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawdaudio/rawdaudio llc-beta /MultiSource/Benchmarks/mediabench/adpcm/rawcaudio/rawcaudio llc-beta /MultiSource/Benchmarks/mediabench/g721/g721encode/encode llc-beta /MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg and probably others, with -regalloc=local. llvm-svn: 28761
* Fix spilling and reloading of CR regs to reload the right values. This fixesChris Lattner2006-06-121-2/+24
| | | | | | Olden/power (and probably others) with -regalloc=local. llvm-svn: 28760
* getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.Evan Cheng2006-05-181-0/+67
| | | | llvm-svn: 28378
* Fix the PowerPC JIT-only failure on UnitTests/Vector/sumarray-dbl, which isChris Lattner2006-05-101-2/+2
| | | | | | | really a bad codegen bug that LLC happens to get lucky with. I must chat with Nate for the proper fix. llvm-svn: 28213
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-4/+4
| | | | llvm-svn: 28102
* There shalt be only one "immediate" operand type!Chris Lattner2006-05-041-13/+12
| | | | llvm-svn: 28099
* Revert Nate's CR patch from last night, which caused many regressions (e.g. ↵Chris Lattner2006-05-041-8/+6
| | | | | | | | | fhourstones). Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of CRRC seems to cause failures as well. Further investigation is required. llvm-svn: 28097
* Since we don't handle callee-save CRs right yet, don't allocate them. AlsoNate Begeman2006-05-021-6/+8
| | | | | | don't step on R11 in the middle of a function when saving and restoring CRs llvm-svn: 28058
* Don't diddle VRSAVE if no registers need to be added/removed from it. ThisChris Lattner2006-04-171-4/+53
| | | | | | | | | | | | | | | | | | | | | | | | allows us to codegen functions as: _test_rol: vspltisw v2, -12 vrlw v2, v2, v2 blr instead of: _test_rol: mfvrsave r2, 256 mr r3, r2 mtvrsave r3 vspltisw v2, -12 vrlw v2, v2, v2 mtvrsave r2 blr Testcase here: CodeGen/PowerPC/vec_vrsave.ll llvm-svn: 27777
* Vectors that are known live-in and live-out are clearly already marked inChris Lattner2006-04-171-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | the vrsave register for the caller. This allows us to codegen a function as: _test_rol: mfspr r2, 256 mr r3, r2 mtspr 256, r3 vspltisw v2, -12 vrlw v2, v2, v2 mtspr 256, r2 blr instead of: _test_rol: mfspr r2, 256 oris r3, r2, 40960 mtspr 256, r3 vspltisw v0, -12 vrlw v2, v0, v0 mtspr 256, r2 blr llvm-svn: 27772
* Move some knowledge about registers out of the code emitter into the ↵Chris Lattner2006-04-171-0/+42
| | | | | | register info. llvm-svn: 27770
* Use a small table instead of macros to do this conversion.Chris Lattner2006-04-171-10/+13
| | | | llvm-svn: 27769
* Fix SingleSource/UnitTests/Vector/sumarray-dblNate Begeman2006-04-111-4/+3
| | | | llvm-svn: 27594
* Fix PR727, correctly handling large stack aligments on ppcNate Begeman2006-04-111-32/+28
| | | | llvm-svn: 27593
* Suppress debug label when not debug.Jim Laskey2006-04-111-1/+1
| | | | llvm-svn: 27588
* Foundation for call frame information.Jim Laskey2006-04-071-2/+29
| | | | llvm-svn: 27491
* Force use of a frame-pointer if there is anything on the stack that is alignedChris Lattner2006-04-031-7/+18
| | | | | | more than the OS keeps the stack aligned. llvm-svn: 27381
* Expose base register for DwarfWriter. Refactor code accordingly.Jim Laskey2006-03-281-9/+2
| | | | llvm-svn: 27225
* Translate llvm target registers to dwarf register numbers properly.Jim Laskey2006-03-271-1/+1
| | | | llvm-svn: 27180
* Add support to locate local variables in frames (early version.)Jim Laskey2006-03-231-0/+12
| | | | llvm-svn: 26994
* When possible, custom lower 32-bit SINT_TO_FP to this:Chris Lattner2006-03-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | _foo2: extsw r2, r3 std r2, -8(r1) lfd f0, -8(r1) fcfid f0, f0 frsp f1, f0 blr instead of this: _foo2: lis r2, ha16(LCPI2_0) lis r4, 17200 xoris r3, r3, 32768 stw r3, -4(r1) stw r4, -8(r1) lfs f0, lo16(LCPI2_0)(r2) lfd f1, -8(r1) fsub f0, f1, f0 frsp f1, f0 blr This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s with llcbeta (16.7% and 38.1% respectively). llvm-svn: 26943
* remove dead variableChris Lattner2006-03-161-2/+0
| | | | llvm-svn: 26813
* teach the ppc backend how to spill/reload vector regsChris Lattner2006-03-161-0/+20
| | | | llvm-svn: 26806
* in functions that use a lot of callee saved regs, this can be more thanChris Lattner2006-03-161-1/+1
| | | | | | 5 instructions away. llvm-svn: 26801
* Add support for copying registers. still needed: spilling and reloading themChris Lattner2006-03-161-0/+2
| | | | llvm-svn: 26800
* For functions that use vector registers, save VRSAVE, mark usedChris Lattner2006-03-131-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers, and update it on entry to each function, then restore it on exit. This compiles: void func(vfloat *a, vfloat *b, vfloat *c) { *a = *b * *c + *c; } to this: _func: mfspr r2, 256 oris r6, r2, 49152 mtspr 256, r6 lvx v0, 0, r5 lvx v1, 0, r4 vmaddfp v0, v1, v0, v0 stvx v0, 0, r3 mtspr 256, r2 blr GCC produces this (which has additional stack accesses): _func: mfspr r0,256 stw r0,-4(r1) oris r0,r0,0xc000 mtspr 256,r0 lvx v0,0,r5 lvx v1,0,r4 lwz r12,-4(r1) vmaddfp v0,v0,v1,v0 stvx v0,0,r3 mtspr 256,r12 blr llvm-svn: 26733
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-18/+0
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) llvm-svn: 25913
* Fix an off-by-one error that Nate's eagle eyes caughtChris Lattner2006-01-111-1/+1
| | | | llvm-svn: 25231
* Use the auto-insert BuildMI constructor to avoid an explicit insert. NoChris Lattner2006-01-111-28/+20
| | | | | | functionality change, just code cleanup. llvm-svn: 25230
* If a function has a non-zero sized frame, use an add to adjust the stackChris Lattner2006-01-111-9/+20
| | | | | | pointer in the epilog, not a load. llvm-svn: 25229
* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-2/+1
| | | | | | hasInFlag, hasOutFlag. llvm-svn: 25155
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-1/+2
| | | | | | | | * Added a pseudo instruction (for each target) that represent "return void". This is a workaround for lack of optional flag operand (return void is not lowered so it does not have a flag operand.) llvm-svn: 24997
* Add the necessary support to the ISel to allow targets to codegen the newNate Begeman2005-11-061-3/+26
| | | | | | | | alignment information appropriately. Includes code for PowerPC to support fixed-size allocas with alignment larger than the stack. Support for arbitrarily aligned dynamic allocas coming soon. llvm-svn: 24224
* Fix the JIT encoding of LWA, LD, STD, and STDU.Chris Lattner2005-10-181-0/+9
| | | | llvm-svn: 23787
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-181-17/+33
| | | | | | purely mechanical. llvm-svn: 23778
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-161-22/+22
| | | | | | redundant after the change. llvm-svn: 23759
* Rename PPC32*.h to PPC*.hChris Lattner2005-10-141-0/+346
This completes the grand PPC file renaming llvm-svn: 23745
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