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path: root/llvm/lib/Target/PowerPC/PPCQPXLoadSplat.cpp
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* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* Reformat blank lines.NAKAMURA Takumi2016-06-201-1/+0
| | | | llvm-svn: 273131
* Untabify.NAKAMURA Takumi2016-06-201-6/+6
| | | | llvm-svn: 273129
* [PowerPC/QPX] Fix the load/splat peephole with overlapping readsHal Finkel2016-04-301-1/+9
| | | | | | | | | | | If, in between the splat and the load (which does an implicit splat), there is a read of the splat register, then that register must have another earlier definition. In that case, we can't replace the load's destination register with the splat's destination register. Unfortunately, I don't have a small or non-fragile test case. llvm-svn: 268152
* Add optimization bisect opt-in calls for PowerPC passesAndrew Kaylor2016-04-271-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D19554 llvm-svn: 267769
* [PowerPC] Add a late MI-level pass for QPX load/splat simplificationHal Finkel2016-03-311-0/+156
Chapter 3 of the QPX manual states that, "Scalar floating-point load instructions, defined in the Power ISA, cause a replication of the source data across all elements of the target register." Thus, if we have a load followed by a QPX splat (from the first lane), the splat is redundant. This adds a late MI-level pass to remove the redundant splats in some of these cases (specifically when both occur in the same basic block). This optimization is scheduled just prior to post-RA scheduling. It can't happen before anything that might replace the load with some already-computed quantity (i.e. store-to-load forwarding). llvm-svn: 265047
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