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* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-1/+1
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* add RESTORE_CR and support CR unspillsHal Finkel2011-12-061-1/+1
| | | | llvm-svn: 145961
* update PPC 940 hazard rec. to function in postRA modeHal Finkel2011-12-021-0/+3
| | | | llvm-svn: 145676
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-1/+4
| | | | llvm-svn: 134244
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. llvm-svn: 122541
* whitespaceAndrew Trick2010-12-241-10/+10
| | | | llvm-svn: 122539
* implement support for the MO_DARWIN_STUB TargetOperand flag,Chris Lattner2010-11-141-1/+1
| | | | | | | | and have isel apply to to call operands as required. This allows us to get $stub suffixes on label references on ppc/tiger with the new instprinter, fixing two tests. Only 2 to go. llvm-svn: 119093
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-6/+0
| | | | llvm-svn: 108567
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-17/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. llvm-svn: 108099
* Replace copyRegToReg with copyPhysReg for PowerPC.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | llvm-svn: 108083
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-1/+2
| | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. llvm-svn: 106243
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-1/+2
| | | | | | doesn't have to guess. llvm-svn: 103194
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
| | | | llvm-svn: 102577
* Add PPC specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+6
| | | | llvm-svn: 102325
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-1/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Remove isProfitableToDuplicateIndirectBranch target hook. It is profitableBob Wilson2009-11-301-2/+0
| | | | | | | | | for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. llvm-svn: 90144
* Tail duplicate indirect branches for PowerPC, too.Bob Wilson2009-11-251-0/+2
| | | | | | | With the testcase for pr3120, the "threaded interpreter" runtime decreases from 1788 to 1413 with this change. llvm-svn: 89877
* Revert the kludge in 76703. I got a cleanDale Johannesen2009-10-121-7/+0
| | | | | | | | | bootstrap of FSF-style PPC, so there is some reason to believe the original bug (which was never analyzed) has been fixed, probably by 82266. llvm-svn: 83871
* Remove unused member functions.Eli Friedman2009-07-241-10/+0
| | | | llvm-svn: 76960
* Let each target determines whether a machine instruction is dead. If true, ↵Evan Cheng2009-07-221-0/+7
| | | | | | | | that allows late codeine passes to delete it. This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround. llvm-svn: 76703
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-1/+1
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-1/+2
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-4/+0
| | | | llvm-svn: 63938
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-6/+5
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-9/+9
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+4
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-5/+5
| | | | llvm-svn: 57622
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-1/+1
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+4
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-2/+4
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-1/+1
| | | | | | (commuted) instruction. llvm-svn: 52308
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-141-1/+1
| | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. llvm-svn: 51091
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+5
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | llvm-svn: 48801
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-0/+7
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+4
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+15
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-5/+26
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+5
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-4/+4
| | | | | | / inserted. llvm-svn: 37192
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-7/+0
| | | | llvm-svn: 33537
* start using PPC predicates more consistently.Chris Lattner2006-11-171-16/+0
| | | | llvm-svn: 31833
* implement the BlockHasNoFallThrough hookChris Lattner2006-10-281-0/+1
| | | | llvm-svn: 31264
* expose DWARF_LABEL opcode# so the branch folder can update debug info properly.Chris Lattner2006-10-171-0/+7
| | | | llvm-svn: 31024
* implement branch inspection/modification methods.Chris Lattner2006-10-131-0/+13
| | | | llvm-svn: 30946
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