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path: root/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-2/+4
| | | | llvm-svn: 103193
* No-ops emitted for scheduling don't correspond with anything in theDan Gohman2010-05-051-2/+0
| | | | | | user's source, so don't arbitrarily assign them a debug location. llvm-svn: 103121
* Frame index can be negative.Evan Cheng2010-04-291-1/+1
| | | | llvm-svn: 102577
* Add PPC specific emitFrameIndexDebugValue.Evan Cheng2010-04-261-0/+10
| | | | llvm-svn: 102325
* EnablePPC64RS and EnablePPC32RS are used in multiple files, so theyDan Gohman2010-04-151-1/+4
| | | | | | can't be static. llvm-svn: 101377
* Educate GetInstrSizeInBytes implementations thatDale Johannesen2010-04-071-0/+1
| | | | | | DBG_VALUE does not generate code. llvm-svn: 100681
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-5/+5
| | | | llvm-svn: 100214
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
| | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. llvm-svn: 100168
* Merge PPC instructions FMRS and FMRD into a single FMR instruction.Jakob Stoklund Olesen2010-02-261-8/+6
| | | | | | | | | This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so fextend has a pattern. Also allow folding of memory operands on FMRSD. llvm-svn: 97275
* Use the right floating point load/store instructions in ↵Jakob Stoklund Olesen2010-02-261-24/+14
| | | | | | | | | | | | | | | | | | PPCInstrInfo::foldMemoryOperandImpl(). The PowerPC floating point registers can represent both f32 and f64 via the two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to allow cross-class coalescing. This coalescing only affects whether registers are spilled as f32 or f64. Spill slots must be accessed with load/store instructions corresponding to the class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking at the instruction opcode which is wrong. X86 has similar floating point register classes, but doesn't try to fold memory operands, so there is no problem there. llvm-svn: 97262
* When save/restoring CR at prolog/epilog, in a largeDale Johannesen2010-02-121-14/+30
| | | | | | | | | | | | | | | | | stack frame, the prolog/epilog code was using the same register for the copy of CR and the address of the save slot. Oops. This is fixed here for Darwin, sort of, by reserving R2 for this case. A better way would be to do the store before the decrement of SP, which is safe on Darwin due to the red zone. SVR4 probably has the same problem, but I don't know how to fix it; there is no red zone and R2 is already used for something else. I'm going to leave it to someone interested in that target. Better still would be to rewrite the CR-saving code completely; spilling each CR subregister individually is horrible code. llvm-svn: 96015
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-12/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-2/+2
| | | | llvm-svn: 79763
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-1/+1
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* Remove unused member functions.Eli Friedman2009-07-241-72/+0
| | | | llvm-svn: 76960
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-4/+4
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-8/+6
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Various small changes related to the Condition Register on PowerPC.Tilmann Scheller2009-07-031-16/+32
| | | | | | | | Don't spill to the CR save area when using the SVR4 ABI for now. Don't rely on constants assigned for registers to be in order (they aren't assigned in order). Make sure CR bits are mapped to the corresponding CR field. llvm-svn: 74767
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-8/+28
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. llvm-svn: 74580
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-21/+43
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* PPC::B and PPC::BCC's target operand may be an immediate.Evan Cheng2009-05-081-0/+9
| | | | llvm-svn: 71282
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | llvm-svn: 64891
* Remove refs to non-DebugLoc version of BuildMI from PowerPC.Dale Johannesen2009-02-131-4/+6
| | | | llvm-svn: 64431
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-16/+19
| | | | | | Modify callers. llvm-svn: 64409
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-37/+46
| | | | llvm-svn: 64342
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-2/+4
| | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. llvm-svn: 64124
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-10/+0
| | | | llvm-svn: 63938
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-1/+5
| | | | | | sub-register indices as well. llvm-svn: 62600
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-4/+4
| | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. llvm-svn: 60488
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-2/+2
| | | | llvm-svn: 59542
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-4/+4
| | | | llvm-svn: 57622
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-23/+23
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Remove isImm(), isReg(), and friends, in favor of Dan Gohman2008-09-131-4/+4
| | | | | | | | | isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. llvm-svn: 56189
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-5/+7
| | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. llvm-svn: 55375
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+3
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. llvm-svn: 54802
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-47/+55
| | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. llvm-svn: 53212
* - Remove calls to copyKillDeadInfo which is an N^2 function. Instead, ↵Evan Cheng2008-07-031-10/+27
| | | | | | | | propagate kill / dead markers as new instructions are constructed in foldMemoryOperand, convertToThressAddress, etc. - Also remove LiveVariables::instructionChanged, etc. Replace all calls with cheaper calls which update VarInfo kill list. llvm-svn: 53097
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-2/+3
| | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. llvm-svn: 52943
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-5/+23
| | | | | | (commuted) instruction. llvm-svn: 52308
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+19
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* detabify llvm, patch by Mike Stump!Chris Lattner2008-03-201-1/+1
| | | | llvm-svn: 48577
* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-46/+51
| | | | | | scavenging for 32-bit and 64-bit separately. llvm-svn: 48186
* fix 80 col violations.Chris Lattner2008-03-101-8/+8
| | | | llvm-svn: 48166
* Stylistic modifications. No functionality changes.Nicolas Geoffray2008-03-101-44/+39
| | | | llvm-svn: 48158
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-0/+56
| | | | llvm-svn: 48143
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-041-7/+8
| | | | llvm-svn: 47915
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-31/+54
| | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. llvm-svn: 47863
* commuteInstr() can now commute non-ssa machine instrs.Evan Cheng2008-02-131-0/+10
| | | | llvm-svn: 47043
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+3
| | | | | | the load address first to make sure it's 16 byte aligned. llvm-svn: 46893
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | llvm-svn: 45679
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